diff options
author | Sunny He <suhe@nvidia.com> | 2017-08-01 18:03:26 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-08-21 16:06:04 -0400 |
commit | b50b379c192714d0d08c3f2d33e90c95cf795253 (patch) | |
tree | bd7786d1fec51f168a9393fcb16a8fe56ad25044 /drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |
parent | 192f1039e11893b9216819837eee871612225849 (diff) |
gpu: nvgpu: Move non-fp pmu members from gpu_ops
Move non-function pointer members out of the pmu and pmu_ver
substructs of gpu_ops. Ideally gpu_ops will have only function
ponters, better matching its intended purpose and improving
readability.
- g.ops.pmu_ver.cmd_id_zbc_table_update has been changed to
g.pmu_ver_cmd_id_zbc_table_update
- g.ops.pmu.lspmuwprinitdone has been changed to
g.pmu_lsf_pmu_wpr_init_done
- g.ops.pmu.lsfloadedfalconid has been changed to
g.pmu_lsf_loaded_falcon_id
Boolean flags have been implemented using the enabled.h API
- g.ops.pmu_ver.is_pmu_zbc_save_supported moved to
common flag NVGPU_PMU_ZBC_SAVE
- g.ops.pmu.fecsbootstrapdone moved to
common flag NVGPU_PMU_FECS_BOOTSTRAP_DONE
Jira NVGPU-74
Change-Id: I08fb20f8f382277f2c579f06d561914c000ea6e0
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1530981
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/gr_gm20b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index 56ebc8ca..5fcc3f7b 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -755,8 +755,8 @@ static int gr_gm20b_load_ctxsw_ucode(struct gk20a *g) | |||
755 | } | 755 | } |
756 | 756 | ||
757 | flags = PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES; | 757 | flags = PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES; |
758 | g->ops.pmu.lsfloadedfalconid = 0; | 758 | g->pmu_lsf_loaded_falcon_id = 0; |
759 | if (g->ops.pmu.fecsbootstrapdone) { | 759 | if (nvgpu_is_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE)) { |
760 | /* this must be recovery so bootstrap fecs and gpccs */ | 760 | /* this must be recovery so bootstrap fecs and gpccs */ |
761 | if (!nvgpu_is_enabled(g, NVGPU_SEC_SECUREGPCCS)) { | 761 | if (!nvgpu_is_enabled(g, NVGPU_SEC_SECUREGPCCS)) { |
762 | gr_gm20b_load_gpccs_with_bootloader(g); | 762 | gr_gm20b_load_gpccs_with_bootloader(g); |
@@ -776,7 +776,7 @@ static int gr_gm20b_load_ctxsw_ucode(struct gk20a *g) | |||
776 | 776 | ||
777 | } else { | 777 | } else { |
778 | /* cold boot or rg exit */ | 778 | /* cold boot or rg exit */ |
779 | g->ops.pmu.fecsbootstrapdone = true; | 779 | __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, true); |
780 | if (!nvgpu_is_enabled(g, NVGPU_SEC_SECUREGPCCS)) { | 780 | if (!nvgpu_is_enabled(g, NVGPU_SEC_SECUREGPCCS)) { |
781 | gr_gm20b_load_gpccs_with_bootloader(g); | 781 | gr_gm20b_load_gpccs_with_bootloader(g); |
782 | } else { | 782 | } else { |