gpu: nvgpu: Add CDE bits in FECS header

In case of CDE channel, T1 (Tex) unit needs to be promoted to 128B
aligned, otherwise causes a HW deadlock. Gpu driver makes changes in
FECS header which FECS uses to configure the T1 promotions to aligned
128B accesses.

Bug 200096226

Change-Id: I8a8deaf6fb91f4bbceacd491db7eb6f7bca5001b
Signed-off-by: sujeet baranwal <sbaranwal@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Signed-off-by: sujeet baranwal <sbaranwal@nvidia.com>
Reviewed-on: http://git-master/r/804625
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 10 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
index 17b4b8ea..df7f2af9 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
@@ -1052,6 +1052,15 @@ static void gr_gm20b_init_cyclestats(struct gk20a *g)
 #endif
 }
 
+void gr_gm20b_enable_cde_in_fecs(void *ctx_ptr)
+{
+        u32 cde_v;
+        
+        cde_v = gk20a_mem_rd32(ctx_ptr + ctxsw_prog_main_image_ctl_o(), 0);
+        cde_v |=  ctxsw_prog_main_image_ctl_cde_enabled_f();
+        gk20a_mem_wr32(ctx_ptr + ctxsw_prog_main_image_ctl_o(), 0, cde_v);
+}
+
 void gm20b_init_gr(struct gpu_ops *gops)
 {
         gops->gr.init_gpc_mmu = gr_gm20b_init_gpc_mmu;
@@ -1107,4 +1116,5 @@ void gm20b_init_gr(struct gpu_ops *gops)
         gops->gr.init_sm_dsm_reg_info = gr_gm20b_init_sm_dsm_reg_info;
         gops->gr.wait_empty = gr_gk20a_wait_idle;
         gops->gr.init_cyclestats = gr_gm20b_init_cyclestats;
+        gops->gr.enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs;
 }