gpu: nvgpu: optimize fecs status polling

bug 200078367

using udelay for fecs status polling
during GR init phase brings down fecs
transaction time to < 20usec from few
hundred usec.

Change-Id: I61a27daaf1187ac086a42779b46aa3fbee3b37f2
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/691918
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 3 insertions, 4 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
index 5b49ba8b..84391377 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
@@ -1,7 +1,7 @@
 /*
  * GM20B GPC MMU
  *
- * Copyright (c) 2011-2014, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011-2015, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -672,7 +672,7 @@ static void gr_gm20b_load_gpccs_with_bootloader(struct gk20a *g)
 static int gr_gm20b_ctx_wait_lsf_ready(struct gk20a *g, u32 timeout, u32 val)
 {
         unsigned long end_jiffies = jiffies + msecs_to_jiffies(timeout);
-        unsigned long delay = GR_IDLE_CHECK_DEFAULT;
+        unsigned long delay = GR_FECS_POLL_INTERVAL;
         u32 reg;
 
         gk20a_dbg_fn("");
@@ -681,8 +681,7 @@ static int gr_gm20b_ctx_wait_lsf_ready(struct gk20a *g, u32 timeout, u32 val)
                 reg = gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(0));
                 if (reg == val)
                         return 0;
-                usleep_range(delay, delay * 2);
-                delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX);
+                udelay(delay);
         } while (time_before(jiffies, end_jiffies) ||
                         !tegra_platform_is_silicon());