gpu: nvgpu: fix fpb_en_mask

In gr_gm20b_get_fbp_en_mask(), we read incorrect fuse register to get status
of enabled FBPs
And then we use incorrect arithmetic to calculate fpb_en_mask

Fix this by using correct fuse register and also doing correct arithmetic to get
mask of enabled FBPs

Bug 200398811
Jira NVGPU-556

Change-Id: I79f3ebf590faa9baf176c7a939142c379bf5ebf4
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1690029
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 11 insertions, 5 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
index 262957c5..1c966c22 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
@@ -1073,16 +1073,22 @@ int gr_gm20b_update_pc_sampling(struct channel_gk20a *c,
 
 u32 gr_gm20b_get_fbp_en_mask(struct gk20a *g)
 {
-        u32 fbp_en_mask, opt_fbio;
+        u32 fbp_en_mask;
         u32 tmp, max_fbps_count;
 
         tmp = gk20a_readl(g, top_num_fbps_r());
         max_fbps_count = top_num_fbps_value_v(tmp);
 
-        opt_fbio = gk20a_readl(g, fuse_status_opt_fbio_r());
-        fbp_en_mask =
-                ((1 << max_fbps_count) - 1) ^
-                fuse_status_opt_fbio_data_v(opt_fbio);
+        /*
+         * Read active fbp mask from fuse
+         * Note that 0:enable and 1:disable in value read from fuse so we've to
+         * flip the bits.
+         * Also set unused bits to zero
+         */
+        fbp_en_mask = gk20a_readl(g, fuse_status_opt_fbp_r());
+        fbp_en_mask = ~fbp_en_mask;
+        fbp_en_mask = fbp_en_mask & ((1 << max_fbps_count) - 1);
+
         return fbp_en_mask;
 }