diff options
author | Vijayakumar <vsubbu@nvidia.com> | 2014-08-22 07:52:57 -0400 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-03-18 15:11:04 -0400 |
commit | a52a50d407d6ac4b6f64c8b71e93d6cbd028e5f7 (patch) | |
tree | b2aded4cb4f19a14fa0443bc587a6164c234ac30 /drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |
parent | 08983f727f0f3574aebb07027060b75e5b6dac6c (diff) |
gpu: nvgpu: gm20b: dynamically detect priv security for secure boot of falcon
based on the config setting and fuse secure no non secure boot is done
Change-Id: I5937ba945c5a3a86f72e0f2a9078fcde01977137
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/487684
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/gr_gm20b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 27 |
1 files changed, 16 insertions, 11 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index c9c32b9f..7949405c 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -31,12 +31,11 @@ static void gr_gm20b_init_gpc_mmu(struct gk20a *g) | |||
31 | 31 | ||
32 | gk20a_dbg_info("initialize gpc mmu"); | 32 | gk20a_dbg_info("initialize gpc mmu"); |
33 | 33 | ||
34 | #ifndef CONFIG_TEGRA_ACR | 34 | if (!g->ops.privsecurity) { |
35 | /* Bypass MMU check for non-secure boot. For | 35 | /* Bypass MMU check for non-secure boot. For |
36 | * secure-boot,this register write has no-effect */ | 36 | * secure-boot,this register write has no-effect */ |
37 | gk20a_writel(g, fb_priv_mmu_phy_secure_r(), 0xffffffff); | 37 | gk20a_writel(g, fb_priv_mmu_phy_secure_r(), 0xffffffff); |
38 | #endif | 38 | } |
39 | |||
40 | temp = gk20a_readl(g, fb_mmu_ctrl_r()); | 39 | temp = gk20a_readl(g, fb_mmu_ctrl_r()); |
41 | temp &= gr_gpcs_pri_mmu_ctrl_vm_pg_size_m() | | 40 | temp &= gr_gpcs_pri_mmu_ctrl_vm_pg_size_m() | |
42 | gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m() | | 41 | gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m() | |
@@ -722,6 +721,13 @@ static int gr_gm20b_load_ctxsw_ucode(struct gk20a *g) | |||
722 | 721 | ||
723 | return 0; | 722 | return 0; |
724 | } | 723 | } |
724 | #else | ||
725 | |||
726 | static int gr_gm20b_load_ctxsw_ucode(struct gk20a *g) | ||
727 | { | ||
728 | return -EPERM; | ||
729 | } | ||
730 | |||
725 | #endif | 731 | #endif |
726 | 732 | ||
727 | void gm20b_init_gr(struct gpu_ops *gops) | 733 | void gm20b_init_gr(struct gpu_ops *gops) |
@@ -745,11 +751,10 @@ void gm20b_init_gr(struct gpu_ops *gops) | |||
745 | gops->gr.init_fs_state = gr_gm20b_ctx_state_floorsweep; | 751 | gops->gr.init_fs_state = gr_gm20b_ctx_state_floorsweep; |
746 | gops->gr.set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask; | 752 | gops->gr.set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask; |
747 | gops->gr.falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments; | 753 | gops->gr.falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments; |
748 | #ifdef CONFIG_TEGRA_ACR | 754 | if (gops->privsecurity) |
749 | gops->gr.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode; | 755 | gops->gr.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode; |
750 | #else | 756 | else |
751 | gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode; | 757 | gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode; |
752 | #endif | ||
753 | gops->gr.get_gpc_tpc_mask = gr_gm20b_get_gpc_tpc_mask; | 758 | gops->gr.get_gpc_tpc_mask = gr_gm20b_get_gpc_tpc_mask; |
754 | gops->gr.free_channel_ctx = gk20a_free_channel_ctx; | 759 | gops->gr.free_channel_ctx = gk20a_free_channel_ctx; |
755 | gops->gr.alloc_obj_ctx = gk20a_alloc_obj_ctx; | 760 | gops->gr.alloc_obj_ctx = gk20a_alloc_obj_ctx; |