gpu: nvgpu: fix zcull programming

There are eight tiles per map tile register and
depending on how many tpcs are present, there is
a chance that s/w will be accessing un-allocated
memory for reading tile values from temp buffers.

Bug 1735760

Change-Id: I5c0e09ec75099aaf6ad03dde964b9e93c2dc2408
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1221580
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 1 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
index c2aa64ba..275224e7 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
@@ -1566,4 +1566,5 @@ void gm20b_init_gr(struct gpu_ops *gops)
         gops->gr.is_ltcn_ltss_addr = gr_gm20b_is_ltcn_ltss_addr;
         gops->gr.split_lts_broadcast_addr = gr_gm20b_split_lts_broadcast_addr;
         gops->gr.split_ltc_broadcast_addr = gr_gm20b_split_ltc_broadcast_addr;
+        gops->gr.program_zcull_mapping = gr_gk20a_program_zcull_mapping;
 }