gpu: nvgpu: use common nvgpu mutex/spinlock APIs

Instead of using Linux APIs for mutex and spinlocks
directly, use new APIs defined in <nvgpu/lock.h>

Replace Linux specific mutex/spinlock declaration,
init, lock, unlock APIs with new APIs
e.g
struct mutex is replaced by struct nvgpu_mutex and
mutex_lock() is replaced by nvgpu_mutex_acquire()

And also include <nvgpu/lock.h> instead of including
<linux/mutex.h> and <linux/spinlock.h>

Add explicit nvgpu/lock.h includes to below
files to fix complilation failures.
gk20a/platform_gk20a.h
include/nvgpu/allocator.h

Jira NVGPU-13

Change-Id: I81a05d21ecdbd90c2076a9f0aefd0e40b215bd33
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1293187
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 6 insertions, 6 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
index 0375d71f..9cf644fd 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
@@ -1247,7 +1247,7 @@ static int gm20b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc)
                                                GPU_LIT_TPC_IN_GPC_STRIDE);
         u32 offset = gpc_stride * gpc + tpc_in_gpc_stride * tpc;
 
-        mutex_lock(&g->dbg_sessions_lock);
+        nvgpu_mutex_acquire(&g->dbg_sessions_lock);
 
         sm_id = gr_gpc0_tpc0_sm_cfg_sm_id_v(gk20a_readl(g,
                         gr_gpc0_tpc0_sm_cfg_r() + offset));
@@ -1263,7 +1263,7 @@ static int gm20b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc)
         gr->sm_error_states[sm_id].hww_warp_esr_report_mask = gk20a_readl(g,
                         gr_gpc0_tpc0_sm_hww_warp_esr_report_mask_r() + offset);
 
-        mutex_unlock(&g->dbg_sessions_lock);
+        nvgpu_mutex_release(&g->dbg_sessions_lock);
 
         return 0;
 }
@@ -1280,7 +1280,7 @@ static int gm20b_gr_update_sm_error_state(struct gk20a *g,
                                                GPU_LIT_TPC_IN_GPC_STRIDE);
         int err = 0;
 
-        mutex_lock(&g->dbg_sessions_lock);
+        nvgpu_mutex_acquire(&g->dbg_sessions_lock);
 
         gr->sm_error_states[sm_id].hww_global_esr =
                         sm_error_state->hww_global_esr;
@@ -1336,7 +1336,7 @@ enable_ctxsw:
         err = gr_gk20a_enable_ctxsw(g);
 
 fail:
-        mutex_unlock(&g->dbg_sessions_lock);
+        nvgpu_mutex_release(&g->dbg_sessions_lock);
         return err;
 }
 
@@ -1351,7 +1351,7 @@ static int gm20b_gr_clear_sm_error_state(struct gk20a *g,
                                                GPU_LIT_TPC_IN_GPC_STRIDE);
         int err = 0;
 
-        mutex_lock(&g->dbg_sessions_lock);
+        nvgpu_mutex_acquire(&g->dbg_sessions_lock);
 
         memset(&gr->sm_error_states[sm_id], 0, sizeof(*gr->sm_error_states));
 
@@ -1377,7 +1377,7 @@ static int gm20b_gr_clear_sm_error_state(struct gk20a *g,
         err = gr_gk20a_enable_ctxsw(g);
 
 fail:
-        mutex_unlock(&g->dbg_sessions_lock);
+        nvgpu_mutex_release(&g->dbg_sessions_lock);
         return err;
 }