gpu: nvgpu: gm20b: Add tile caching registers

Add tile caching related registers to access map.

Bug 1692373

Change-Id: I4516812dd571bed3be2dfa2b210abe3177e794fe
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/812354

1 files changed, 24 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
index 81067f0a..d6f56d78 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
@@ -1133,7 +1133,31 @@ static void gr_gm20b_get_access_map(struct gk20a *g,
         static u32 wl_addr_gm20b[] = {
                 /* this list must be sorted (low to high) */
                 0x404468, /* gr_pri_mme_max_instructions       */
+                0x418300, /* gr_pri_gpcs_rasterarb_line_class  */
                 0x418800, /* gr_pri_gpcs_setup_debug           */
+                0x418e00, /* gr_pri_gpcs_swdx_config           */
+                0x418e40, /* gr_pri_gpcs_swdx_tc_bundle_ctrl   */
+                0x418e44, /* gr_pri_gpcs_swdx_tc_bundle_ctrl   */
+                0x418e48, /* gr_pri_gpcs_swdx_tc_bundle_ctrl   */
+                0x418e4c, /* gr_pri_gpcs_swdx_tc_bundle_ctrl   */
+                0x418e50, /* gr_pri_gpcs_swdx_tc_bundle_ctrl   */
+                0x418e58, /* gr_pri_gpcs_swdx_tc_bundle_addr   */
+                0x418e5c, /* gr_pri_gpcs_swdx_tc_bundle_addr   */
+                0x418e60, /* gr_pri_gpcs_swdx_tc_bundle_addr   */
+                0x418e64, /* gr_pri_gpcs_swdx_tc_bundle_addr   */
+                0x418e68, /* gr_pri_gpcs_swdx_tc_bundle_addr   */
+                0x418e6c, /* gr_pri_gpcs_swdx_tc_bundle_addr   */
+                0x418e70, /* gr_pri_gpcs_swdx_tc_bundle_addr   */
+                0x418e74, /* gr_pri_gpcs_swdx_tc_bundle_addr   */
+                0x418e78, /* gr_pri_gpcs_swdx_tc_bundle_addr   */
+                0x418e7c, /* gr_pri_gpcs_swdx_tc_bundle_addr   */
+                0x418e80, /* gr_pri_gpcs_swdx_tc_bundle_addr   */
+                0x418e84, /* gr_pri_gpcs_swdx_tc_bundle_addr   */
+                0x418e88, /* gr_pri_gpcs_swdx_tc_bundle_addr   */
+                0x418e8c, /* gr_pri_gpcs_swdx_tc_bundle_addr   */
+                0x418e90, /* gr_pri_gpcs_swdx_tc_bundle_addr   */
+                0x418e94, /* gr_pri_gpcs_swdx_tc_bundle_addr   */
+                0x419864, /* gr_pri_gpcs_tpcs_pe_l2_evict_policy */
                 0x419a04, /* gr_pri_gpcs_tpcs_tex_lod_dbg      */
                 0x419a08, /* gr_pri_gpcs_tpcs_tex_samp_dbg     */
                 0x419e10, /* gr_pri_gpcs_tpcs_sm_dbgr_control0 */