gpu: nvgpu: use fuse APIs from <nvgpu/fuse.h>

Remove <soc/tegra/fuse.h> includes and include
<nvgpu/fuse.h> header to remove direct dependency
on platform specific header

Use specific APIs like below to read/write fuses
nvgpu_tegra_fuse_write_bypass()
nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable()

Remove old code which was compiled for kernel versions
less than 4.4 since we support only k4.4 and greater
versions now

Jira NVGPU-75

Change-Id: Iddd8e1a8da7effbce2aff217e8e25f7de04962d6
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1497518
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

1 files changed, 9 insertions, 10 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
index c6e451e1..b7fb1ac5 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
@@ -13,14 +13,13 @@
  * more details.
  */
 
-#include <soc/tegra/fuse.h>
-
 #include <dt-bindings/soc/gm20b-fuse.h>
 
 #include <nvgpu/kmem.h>
 #include <nvgpu/log.h>
 #include <nvgpu/enabled.h>
 #include <nvgpu/debug.h>
+#include <nvgpu/fuse.h>
 
 #include "gk20a/gk20a.h"
 #include "gk20a/gr_gk20a.h"
@@ -548,18 +547,18 @@ static u32 gr_gm20b_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index)
 
 static void gr_gm20b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index)
 {
-        tegra_fuse_control_write(0x1, FUSE_FUSEBYPASS_0);
-        tegra_fuse_control_write(0x0, FUSE_WRITE_ACCESS_SW_0);
+        nvgpu_tegra_fuse_write_bypass(0x1);
+        nvgpu_tegra_fuse_write_access_sw(0x0);
 
         if (g->gr.gpc_tpc_mask[gpc_index] == 0x1) {
-                tegra_fuse_control_write(0x0, FUSE_OPT_GPU_TPC0_DISABLE_0);
-                tegra_fuse_control_write(0x1, FUSE_OPT_GPU_TPC1_DISABLE_0);
+                nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(0x0);
+                nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(0x1);
         } else if (g->gr.gpc_tpc_mask[gpc_index] == 0x2) {
-                tegra_fuse_control_write(0x1, FUSE_OPT_GPU_TPC0_DISABLE_0);
-                tegra_fuse_control_write(0x0, FUSE_OPT_GPU_TPC1_DISABLE_0);
+                nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(0x1);
+                nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(0x0);
         } else {
-                tegra_fuse_control_write(0x0, FUSE_OPT_GPU_TPC0_DISABLE_0);
-                tegra_fuse_control_write(0x0, FUSE_OPT_GPU_TPC1_DISABLE_0);
+                nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(0x0);
+                nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(0x0);
         }
 }