gpu: nvgpu: Remove direct HW access from ctrl_gk20a.c

ctrl_gk20a.c had some direct accesses to hardware. These violate the
HAL rules, because we don't have per-GPU ctrl, and thus the code
cannot be made GPU independent.

Move all GR accesses to new GR HALs and use existing bus HAL for
accessing timer. Remove #includes of all hardware headers.

JIRA NVGPU-28

Change-Id: I57e67519f62e9bd6c3e725e1bef6e366190f5834
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1327001
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 6 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
index 4f4b8d4a..a43fcdab 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
@@ -1609,5 +1609,10 @@ void gm20b_init_gr(struct gpu_ops *gops)
         gops->gr.write_pm_ptr = gr_gk20a_write_pm_ptr;
         gops->gr.init_elcg_mode = gr_gk20a_init_elcg_mode;
         gops->gr.load_tpc_mask = gr_gm20b_load_tpc_mask;
-
+        gops->gr.inval_icache = gr_gk20a_inval_icache;
+        gops->gr.trigger_suspend = gr_gk20a_trigger_suspend;
+        gops->gr.wait_for_pause = gr_gk20a_wait_for_pause;
+        gops->gr.resume_from_pause = gr_gk20a_resume_from_pause;
+        gops->gr.clear_sm_errors = gr_gk20a_clear_sm_errors;
+        gops->gr.tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions;
 }