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authorTerje Bergstrom <tbergstrom@nvidia.com>2017-11-07 13:25:07 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2017-11-09 17:27:04 -0500
commit1dad4adbd2aecfd484a84d47b29b81bb665bc60b (patch)
treeafe2829ebef911e8ee4409753a2db7f626897624 /drivers/gpu/nvgpu/gm20b/gr_gm20b.c
parent39527d58855fb7cb7dffef01c4f7290ae3a119ce (diff)
gpu: nvgpu: Move fuse override DT handling
Move fuse override DT handling to Linux code. All the chip specific fuse override functions did the same thing, so delete the HAL and call the same function to read the DT overrides on all chips. Also remove the fuse override functionality from dGPU. There are no DT entries for PCIe devices, so it would've failed anyway. JIRA NVGPU-259 Change-Id: Iba64a5d53bf4eb94198c0408a462620efc2ddde4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1593687 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/gr_gm20b.c')
-rw-r--r--drivers/gpu/nvgpu/gm20b/gr_gm20b.c48
1 files changed, 0 insertions, 48 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
index 7ec8e2cb..afe60b98 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
@@ -22,8 +22,6 @@
22 * DEALINGS IN THE SOFTWARE. 22 * DEALINGS IN THE SOFTWARE.
23 */ 23 */
24 24
25#include <dt-bindings/soc/gm20b-fuse.h>
26
27#include <nvgpu/kmem.h> 25#include <nvgpu/kmem.h>
28#include <nvgpu/log.h> 26#include <nvgpu/log.h>
29#include <nvgpu/enabled.h> 27#include <nvgpu/enabled.h>
@@ -1423,52 +1421,6 @@ int gr_gm20b_get_preemption_mode_flags(struct gk20a *g,
1423 return 0; 1421 return 0;
1424} 1422}
1425 1423
1426int gm20b_gr_tpc_disable_override(struct gk20a *g, u32 mask)
1427{
1428 if (!mask)
1429 return 0;
1430
1431 g->tpc_fs_mask_user = ~mask;
1432
1433 return 0;
1434}
1435
1436int gm20b_gr_fuse_override(struct gk20a *g)
1437{
1438 struct device_node *np = dev_from_gk20a(g)->of_node;
1439 u32 *fuses;
1440 int count, i;
1441
1442 if (!np) /* may be pcie device */
1443 return 0;
1444
1445 count = of_property_count_elems_of_size(np, "fuse-overrides", 8);
1446 if (count <= 0)
1447 return count;
1448
1449 fuses = nvgpu_kmalloc(g, sizeof(u32) * count * 2);
1450 if (!fuses)
1451 return -ENOMEM;
1452 of_property_read_u32_array(np, "fuse-overrides", fuses, count * 2);
1453 for (i = 0; i < count; i++) {
1454 u32 fuse, value;
1455
1456 fuse = fuses[2 * i];
1457 value = fuses[2 * i + 1];
1458 switch (fuse) {
1459 case GM20B_FUSE_OPT_TPC_DISABLE:
1460 gm20b_gr_tpc_disable_override(g, value);
1461 break;
1462 default:
1463 nvgpu_err(g, "ignore unknown fuse override %08x", fuse);
1464 break;
1465 }
1466 }
1467
1468 nvgpu_kfree(g, fuses);
1469 return 0;
1470}
1471
1472bool gr_gm20b_is_ltcs_ltss_addr(struct gk20a *g, u32 addr) 1424bool gr_gm20b_is_ltcs_ltss_addr(struct gk20a *g, u32 addr)
1473{ 1425{
1474 u32 ltc_shared_base = ltc_ltcs_ltss_v(); 1426 u32 ltc_shared_base = ltc_ltcs_ltss_v();