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authorVinod G <vinodg@nvidia.com>2018-05-17 17:43:51 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-05-21 16:55:00 -0400
commitdffeea5deb9754686e60eafec5194b7bf7bb4e77 (patch)
tree20c413a02da8da02ef45335941b142ea790dd2eb /drivers/gpu/nvgpu/gm20b/gm20b_gating_reglist.c
parentbd7489886c0198fb65f939e73ab5e067f09c51b4 (diff)
gpu: nvgpu: Code updates for MISRA violations
As part of the MISRA fixes, moving all the gating_reglist files to common/clock_gating dir, the new directory structure suggested to follow. Removed unused gating_reglist files for gk20a JIRA NVGPU-646 Change-Id: I388855befcf991ee68eeffed10fe9ac456210649 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1722330 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/gm20b_gating_reglist.c')
-rw-r--r--drivers/gpu/nvgpu/gm20b/gm20b_gating_reglist.c731
1 files changed, 0 insertions, 731 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/gm20b_gating_reglist.c b/drivers/gpu/nvgpu/gm20b/gm20b_gating_reglist.c
deleted file mode 100644
index 0ebb2d0d..00000000
--- a/drivers/gpu/nvgpu/gm20b/gm20b_gating_reglist.c
+++ /dev/null
@@ -1,731 +0,0 @@
1/*
2 * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 *
22 * This file is autogenerated. Do not edit.
23 */
24
25#ifndef __gm20b_gating_reglist_h__
26#define __gm20b_gating_reglist_h__
27
28#include "gm20b_gating_reglist.h"
29#include <nvgpu/enabled.h>
30
31struct gating_desc {
32 u32 addr;
33 u32 prod;
34 u32 disable;
35};
36/* slcg bus */
37static const struct gating_desc gm20b_slcg_bus[] = {
38 {.addr = 0x00001c04, .prod = 0x00000000, .disable = 0x000003fe},
39};
40
41/* slcg ce2 */
42static const struct gating_desc gm20b_slcg_ce2[] = {
43 {.addr = 0x00106f28, .prod = 0x00000000, .disable = 0x000007fe},
44};
45
46/* slcg chiplet */
47static const struct gating_desc gm20b_slcg_chiplet[] = {
48 {.addr = 0x0010c07c, .prod = 0x00000000, .disable = 0x00000007},
49 {.addr = 0x0010e07c, .prod = 0x00000000, .disable = 0x00000007},
50 {.addr = 0x0010d07c, .prod = 0x00000000, .disable = 0x00000007},
51 {.addr = 0x0010e17c, .prod = 0x00000000, .disable = 0x00000007},
52};
53
54/* slcg fb */
55static const struct gating_desc gm20b_slcg_fb[] = {
56 {.addr = 0x00100d14, .prod = 0x00000000, .disable = 0xfffffffe},
57 {.addr = 0x00100c9c, .prod = 0x00000000, .disable = 0x000001fe},
58};
59
60/* slcg fifo */
61static const struct gating_desc gm20b_slcg_fifo[] = {
62 {.addr = 0x000026ac, .prod = 0x00000100, .disable = 0x0001fffe},
63};
64
65/* slcg gr */
66static const struct gating_desc gm20b_slcg_gr[] = {
67 {.addr = 0x004041f4, .prod = 0x00000002, .disable = 0x03fffffe},
68 {.addr = 0x0040917c, .prod = 0x00020008, .disable = 0x0003fffe},
69 {.addr = 0x00409894, .prod = 0x00000040, .disable = 0x0003fffe},
70 {.addr = 0x004078c4, .prod = 0x00000000, .disable = 0x000001fe},
71 {.addr = 0x00406004, .prod = 0x00000000, .disable = 0x0001fffe},
72 {.addr = 0x00405864, .prod = 0x00000000, .disable = 0x000001fe},
73 {.addr = 0x00405910, .prod = 0xfffffff0, .disable = 0xfffffffe},
74 {.addr = 0x00408044, .prod = 0x00000000, .disable = 0x000007fe},
75 {.addr = 0x00407004, .prod = 0x00000000, .disable = 0x0000007e},
76 {.addr = 0x0041a17c, .prod = 0x00020008, .disable = 0x0003fffe},
77 {.addr = 0x0041a894, .prod = 0x00000040, .disable = 0x0003fffe},
78 {.addr = 0x00418504, .prod = 0x00000000, .disable = 0x0007fffe},
79 {.addr = 0x0041860c, .prod = 0x00000000, .disable = 0x000001fe},
80 {.addr = 0x0041868c, .prod = 0x00000000, .disable = 0x0000001e},
81 {.addr = 0x0041871c, .prod = 0x00000000, .disable = 0x0000003e},
82 {.addr = 0x00418388, .prod = 0x00000000, .disable = 0x00000001},
83 {.addr = 0x0041882c, .prod = 0x00000000, .disable = 0x0001fffe},
84 {.addr = 0x00418bc0, .prod = 0x00000000, .disable = 0x000001fe},
85 {.addr = 0x00418974, .prod = 0x00000000, .disable = 0x0001fffe},
86 {.addr = 0x00418c74, .prod = 0xffffffc0, .disable = 0xfffffffe},
87 {.addr = 0x00418cf4, .prod = 0xfffffffc, .disable = 0xfffffffe},
88 {.addr = 0x00418d74, .prod = 0xffffffe0, .disable = 0xfffffffe},
89 {.addr = 0x00418f10, .prod = 0xffffffe0, .disable = 0xfffffffe},
90 {.addr = 0x00418e10, .prod = 0xfffffffe, .disable = 0xfffffffe},
91 {.addr = 0x00419024, .prod = 0x000001fe, .disable = 0x000001fe},
92 {.addr = 0x0041889c, .prod = 0x00000000, .disable = 0x000001fe},
93 {.addr = 0x00419d64, .prod = 0x00000000, .disable = 0x000001ff},
94 {.addr = 0x00419a44, .prod = 0x00000000, .disable = 0x0000000e},
95 {.addr = 0x00419a4c, .prod = 0x00000000, .disable = 0x000001fe},
96 {.addr = 0x00419a54, .prod = 0x00000000, .disable = 0x0000003e},
97 {.addr = 0x00419a5c, .prod = 0x00000000, .disable = 0x0000000e},
98 {.addr = 0x00419a64, .prod = 0x00000000, .disable = 0x000001fe},
99 {.addr = 0x00419a6c, .prod = 0x00000000, .disable = 0x0000000e},
100 {.addr = 0x00419a74, .prod = 0x00000000, .disable = 0x0000000e},
101 {.addr = 0x00419a7c, .prod = 0x00000000, .disable = 0x0000003e},
102 {.addr = 0x00419a84, .prod = 0x00000000, .disable = 0x0000000e},
103 {.addr = 0x0041986c, .prod = 0x00000104, .disable = 0x00fffffe},
104 {.addr = 0x00419cd8, .prod = 0x00000000, .disable = 0x001ffffe},
105 {.addr = 0x00419ce0, .prod = 0x00000000, .disable = 0x001ffffe},
106 {.addr = 0x00419c74, .prod = 0x0000001e, .disable = 0x0000001e},
107 {.addr = 0x00419fd4, .prod = 0x00000000, .disable = 0x0003fffe},
108 {.addr = 0x00419fdc, .prod = 0xffedff00, .disable = 0xfffffffe},
109 {.addr = 0x00419fe4, .prod = 0x00001b00, .disable = 0x00001ffe},
110 {.addr = 0x00419ff4, .prod = 0x00000000, .disable = 0x00003ffe},
111 {.addr = 0x00419ffc, .prod = 0x00000000, .disable = 0x0001fffe},
112 {.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe},
113 {.addr = 0x0041bfec, .prod = 0xfffffff0, .disable = 0xfffffffe},
114 {.addr = 0x0041bed4, .prod = 0xfffffff6, .disable = 0xfffffffe},
115 {.addr = 0x00408814, .prod = 0x00000000, .disable = 0x0001fffe},
116 {.addr = 0x0040881c, .prod = 0x00000000, .disable = 0x0001fffe},
117 {.addr = 0x00408a84, .prod = 0x00000000, .disable = 0x0001fffe},
118 {.addr = 0x00408a8c, .prod = 0x00000000, .disable = 0x0001fffe},
119 {.addr = 0x00408a94, .prod = 0x00000000, .disable = 0x0001fffe},
120 {.addr = 0x00408a9c, .prod = 0x00000000, .disable = 0x0001fffe},
121 {.addr = 0x00408aa4, .prod = 0x00000000, .disable = 0x0001fffe},
122 {.addr = 0x00408aac, .prod = 0x00000000, .disable = 0x0001fffe},
123 {.addr = 0x004089ac, .prod = 0x00000000, .disable = 0x0001fffe},
124 {.addr = 0x00408a24, .prod = 0x00000000, .disable = 0x000001ff},
125};
126
127/* slcg ltc */
128static const struct gating_desc gm20b_slcg_ltc[] = {
129 {.addr = 0x0017e050, .prod = 0x00000000, .disable = 0xfffffffe},
130 {.addr = 0x0017e35c, .prod = 0x00000000, .disable = 0xfffffffe},
131};
132
133/* slcg perf */
134static const struct gating_desc gm20b_slcg_perf[] = {
135 {.addr = 0x001be018, .prod = 0x000001ff, .disable = 0x00000000},
136 {.addr = 0x001bc018, .prod = 0x000001ff, .disable = 0x00000000},
137 {.addr = 0x001b8018, .prod = 0x000001ff, .disable = 0x00000000},
138 {.addr = 0x001b4124, .prod = 0x00000001, .disable = 0x00000000},
139};
140
141/* slcg PriRing */
142static const struct gating_desc gm20b_slcg_priring[] = {
143 {.addr = 0x001200a8, .prod = 0x00000000, .disable = 0x00000001},
144};
145
146/* slcg pwr_csb */
147static const struct gating_desc gm20b_slcg_pwr_csb[] = {
148 {.addr = 0x0000017c, .prod = 0x00020008, .disable = 0x0003fffe},
149 {.addr = 0x00000e74, .prod = 0x00000000, .disable = 0x0000000f},
150 {.addr = 0x00000a74, .prod = 0x00000000, .disable = 0x00007ffe},
151 {.addr = 0x000016b8, .prod = 0x00000000, .disable = 0x0000000f},
152};
153
154/* slcg pmu */
155static const struct gating_desc gm20b_slcg_pmu[] = {
156 {.addr = 0x0010a17c, .prod = 0x00020008, .disable = 0x0003fffe},
157 {.addr = 0x0010aa74, .prod = 0x00000000, .disable = 0x00007ffe},
158 {.addr = 0x0010ae74, .prod = 0x00000000, .disable = 0x0000000f},
159};
160
161/* therm gr */
162static const struct gating_desc gm20b_slcg_therm[] = {
163 {.addr = 0x000206b8, .prod = 0x00000000, .disable = 0x0000000f},
164};
165
166/* slcg Xbar */
167static const struct gating_desc gm20b_slcg_xbar[] = {
168 {.addr = 0x0013cbe4, .prod = 0x00000000, .disable = 0x1ffffffe},
169 {.addr = 0x0013cc04, .prod = 0x00000000, .disable = 0x1ffffffe},
170};
171
172/* blcg bus */
173static const struct gating_desc gm20b_blcg_bus[] = {
174 {.addr = 0x00001c00, .prod = 0x00000042, .disable = 0x00000000},
175};
176
177/* blcg ctxsw prog */
178static const struct gating_desc gm20b_blcg_ctxsw_prog[] = {
179};
180
181/* blcg fb */
182static const struct gating_desc gm20b_blcg_fb[] = {
183 {.addr = 0x00100d10, .prod = 0x0000c242, .disable = 0x00000000},
184 {.addr = 0x00100d30, .prod = 0x0000c242, .disable = 0x00000000},
185 {.addr = 0x00100d3c, .prod = 0x00000242, .disable = 0x00000000},
186 {.addr = 0x00100d48, .prod = 0x0000c242, .disable = 0x00000000},
187 {.addr = 0x00100c98, .prod = 0x00000242, .disable = 0x00000000},
188};
189
190/* blcg fifo */
191static const struct gating_desc gm20b_blcg_fifo[] = {
192 {.addr = 0x000026a4, .prod = 0x0000c242, .disable = 0x00000000},
193};
194
195/* blcg gr */
196static const struct gating_desc gm20b_blcg_gr[] = {
197 {.addr = 0x004041f0, .prod = 0x00004046, .disable = 0x00000000},
198 {.addr = 0x00409890, .prod = 0x0000007f, .disable = 0x00000000},
199 {.addr = 0x004098b0, .prod = 0x0000007f, .disable = 0x00000000},
200 {.addr = 0x004078c0, .prod = 0x00000042, .disable = 0x00000000},
201 {.addr = 0x00406000, .prod = 0x00004044, .disable = 0x00000000},
202 {.addr = 0x00405860, .prod = 0x00004042, .disable = 0x00000000},
203 {.addr = 0x0040590c, .prod = 0x00004044, .disable = 0x00000000},
204 {.addr = 0x00408040, .prod = 0x00004044, .disable = 0x00000000},
205 {.addr = 0x00407000, .prod = 0x00004041, .disable = 0x00000000},
206 {.addr = 0x00405bf0, .prod = 0x00004044, .disable = 0x00000000},
207 {.addr = 0x0041a890, .prod = 0x0000007f, .disable = 0x00000000},
208 {.addr = 0x0041a8b0, .prod = 0x0000007f, .disable = 0x00000000},
209 {.addr = 0x00418500, .prod = 0x00004044, .disable = 0x00000000},
210 {.addr = 0x00418608, .prod = 0x00004042, .disable = 0x00000000},
211 {.addr = 0x00418688, .prod = 0x00004042, .disable = 0x00000000},
212 {.addr = 0x00418718, .prod = 0x00000042, .disable = 0x00000000},
213 {.addr = 0x00418828, .prod = 0x00000044, .disable = 0x00000000},
214 {.addr = 0x00418bbc, .prod = 0x00004042, .disable = 0x00000000},
215 {.addr = 0x00418970, .prod = 0x00004042, .disable = 0x00000000},
216 {.addr = 0x00418c70, .prod = 0x00004044, .disable = 0x00000000},
217 {.addr = 0x00418cf0, .prod = 0x00004044, .disable = 0x00000000},
218 {.addr = 0x00418d70, .prod = 0x00004044, .disable = 0x00000000},
219 {.addr = 0x00418f0c, .prod = 0x00004044, .disable = 0x00000000},
220 {.addr = 0x00418e0c, .prod = 0x00004044, .disable = 0x00000000},
221 {.addr = 0x00419020, .prod = 0x00004042, .disable = 0x00000000},
222 {.addr = 0x00419038, .prod = 0x00000042, .disable = 0x00000000},
223 {.addr = 0x00418898, .prod = 0x00000042, .disable = 0x00000000},
224 {.addr = 0x00419a40, .prod = 0x00000042, .disable = 0x00000000},
225 {.addr = 0x00419a48, .prod = 0x00004042, .disable = 0x00000000},
226 {.addr = 0x00419a50, .prod = 0x00004042, .disable = 0x00000000},
227 {.addr = 0x00419a58, .prod = 0x00004042, .disable = 0x00000000},
228 {.addr = 0x00419a60, .prod = 0x00004042, .disable = 0x00000000},
229 {.addr = 0x00419a68, .prod = 0x00004042, .disable = 0x00000000},
230 {.addr = 0x00419a70, .prod = 0x00004042, .disable = 0x00000000},
231 {.addr = 0x00419a78, .prod = 0x00004042, .disable = 0x00000000},
232 {.addr = 0x00419a80, .prod = 0x00004042, .disable = 0x00000000},
233 {.addr = 0x00419868, .prod = 0x00000042, .disable = 0x00000000},
234 {.addr = 0x00419cd4, .prod = 0x00000002, .disable = 0x00000000},
235 {.addr = 0x00419cdc, .prod = 0x00000002, .disable = 0x00000000},
236 {.addr = 0x00419c70, .prod = 0x00004044, .disable = 0x00000000},
237 {.addr = 0x00419fd0, .prod = 0x00004044, .disable = 0x00000000},
238 {.addr = 0x00419fd8, .prod = 0x00004046, .disable = 0x00000000},
239 {.addr = 0x00419fe0, .prod = 0x00004044, .disable = 0x00000000},
240 {.addr = 0x00419fe8, .prod = 0x00000042, .disable = 0x00000000},
241 {.addr = 0x00419ff0, .prod = 0x00004045, .disable = 0x00000000},
242 {.addr = 0x00419ff8, .prod = 0x00000002, .disable = 0x00000000},
243 {.addr = 0x00419f90, .prod = 0x00000002, .disable = 0x00000000},
244 {.addr = 0x0041be28, .prod = 0x00000042, .disable = 0x00000000},
245 {.addr = 0x0041bfe8, .prod = 0x00004044, .disable = 0x00000000},
246 {.addr = 0x0041bed0, .prod = 0x00004044, .disable = 0x00000000},
247 {.addr = 0x00408810, .prod = 0x00004042, .disable = 0x00000000},
248 {.addr = 0x00408818, .prod = 0x00004042, .disable = 0x00000000},
249 {.addr = 0x00408a80, .prod = 0x00004042, .disable = 0x00000000},
250 {.addr = 0x00408a88, .prod = 0x00004042, .disable = 0x00000000},
251 {.addr = 0x00408a90, .prod = 0x00004042, .disable = 0x00000000},
252 {.addr = 0x00408a98, .prod = 0x00004042, .disable = 0x00000000},
253 {.addr = 0x00408aa0, .prod = 0x00004042, .disable = 0x00000000},
254 {.addr = 0x00408aa8, .prod = 0x00004042, .disable = 0x00000000},
255 {.addr = 0x004089a8, .prod = 0x00004042, .disable = 0x00000000},
256 {.addr = 0x004089b0, .prod = 0x00000042, .disable = 0x00000000},
257 {.addr = 0x004089b8, .prod = 0x00004042, .disable = 0x00000000},
258};
259
260/* blcg ltc */
261static const struct gating_desc gm20b_blcg_ltc[] = {
262 {.addr = 0x0017e030, .prod = 0x00000044, .disable = 0x00000000},
263 {.addr = 0x0017e040, .prod = 0x00000044, .disable = 0x00000000},
264 {.addr = 0x0017e3e0, .prod = 0x00000044, .disable = 0x00000000},
265 {.addr = 0x0017e3c8, .prod = 0x00000044, .disable = 0x00000000},
266};
267
268/* blcg pwr_csb */
269static const struct gating_desc gm20b_blcg_pwr_csb[] = {
270 {.addr = 0x00000a70, .prod = 0x00000045, .disable = 0x00000000},
271};
272
273/* blcg pmu */
274static const struct gating_desc gm20b_blcg_pmu[] = {
275 {.addr = 0x0010aa70, .prod = 0x00000045, .disable = 0x00000000},
276};
277
278/* blcg Xbar */
279static const struct gating_desc gm20b_blcg_xbar[] = {
280 {.addr = 0x0013cbe0, .prod = 0x00000042, .disable = 0x00000000},
281 {.addr = 0x0013cc00, .prod = 0x00000042, .disable = 0x00000000},
282};
283
284/* pg gr */
285static const struct gating_desc gm20b_pg_gr[] = {
286};
287
288/* inline functions */
289void gm20b_slcg_bus_load_gating_prod(struct gk20a *g,
290 bool prod)
291{
292 u32 i;
293 u32 size = sizeof(gm20b_slcg_bus) / sizeof(struct gating_desc);
294
295 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
296 return;
297
298 for (i = 0; i < size; i++) {
299 if (prod)
300 gk20a_writel(g, gm20b_slcg_bus[i].addr,
301 gm20b_slcg_bus[i].prod);
302 else
303 gk20a_writel(g, gm20b_slcg_bus[i].addr,
304 gm20b_slcg_bus[i].disable);
305 }
306}
307
308void gm20b_slcg_ce2_load_gating_prod(struct gk20a *g,
309 bool prod)
310{
311 u32 i;
312 u32 size = sizeof(gm20b_slcg_ce2) / sizeof(struct gating_desc);
313
314 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
315 return;
316
317 for (i = 0; i < size; i++) {
318 if (prod)
319 gk20a_writel(g, gm20b_slcg_ce2[i].addr,
320 gm20b_slcg_ce2[i].prod);
321 else
322 gk20a_writel(g, gm20b_slcg_ce2[i].addr,
323 gm20b_slcg_ce2[i].disable);
324 }
325}
326
327void gm20b_slcg_chiplet_load_gating_prod(struct gk20a *g,
328 bool prod)
329{
330 u32 i;
331 u32 size = sizeof(gm20b_slcg_chiplet) / sizeof(struct gating_desc);
332
333 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
334 return;
335
336 for (i = 0; i < size; i++) {
337 if (prod)
338 gk20a_writel(g, gm20b_slcg_chiplet[i].addr,
339 gm20b_slcg_chiplet[i].prod);
340 else
341 gk20a_writel(g, gm20b_slcg_chiplet[i].addr,
342 gm20b_slcg_chiplet[i].disable);
343 }
344}
345
346void gm20b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g,
347 bool prod)
348{
349}
350
351void gm20b_slcg_fb_load_gating_prod(struct gk20a *g,
352 bool prod)
353{
354 u32 i;
355 u32 size = sizeof(gm20b_slcg_fb) / sizeof(struct gating_desc);
356
357 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
358 return;
359
360 for (i = 0; i < size; i++) {
361 if (prod)
362 gk20a_writel(g, gm20b_slcg_fb[i].addr,
363 gm20b_slcg_fb[i].prod);
364 else
365 gk20a_writel(g, gm20b_slcg_fb[i].addr,
366 gm20b_slcg_fb[i].disable);
367 }
368}
369
370void gm20b_slcg_fifo_load_gating_prod(struct gk20a *g,
371 bool prod)
372{
373 u32 i;
374 u32 size = sizeof(gm20b_slcg_fifo) / sizeof(struct gating_desc);
375
376 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
377 return;
378
379 for (i = 0; i < size; i++) {
380 if (prod)
381 gk20a_writel(g, gm20b_slcg_fifo[i].addr,
382 gm20b_slcg_fifo[i].prod);
383 else
384 gk20a_writel(g, gm20b_slcg_fifo[i].addr,
385 gm20b_slcg_fifo[i].disable);
386 }
387}
388
389void gr_gm20b_slcg_gr_load_gating_prod(struct gk20a *g,
390 bool prod)
391{
392 u32 i;
393 u32 size = sizeof(gm20b_slcg_gr) / sizeof(struct gating_desc);
394
395 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
396 return;
397
398 for (i = 0; i < size; i++) {
399 if (prod)
400 gk20a_writel(g, gm20b_slcg_gr[i].addr,
401 gm20b_slcg_gr[i].prod);
402 else
403 gk20a_writel(g, gm20b_slcg_gr[i].addr,
404 gm20b_slcg_gr[i].disable);
405 }
406}
407
408void ltc_gm20b_slcg_ltc_load_gating_prod(struct gk20a *g,
409 bool prod)
410{
411 u32 i;
412 u32 size = sizeof(gm20b_slcg_ltc) / sizeof(struct gating_desc);
413
414 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
415 return;
416
417 for (i = 0; i < size; i++) {
418 if (prod)
419 gk20a_writel(g, gm20b_slcg_ltc[i].addr,
420 gm20b_slcg_ltc[i].prod);
421 else
422 gk20a_writel(g, gm20b_slcg_ltc[i].addr,
423 gm20b_slcg_ltc[i].disable);
424 }
425}
426
427void gm20b_slcg_perf_load_gating_prod(struct gk20a *g,
428 bool prod)
429{
430 u32 i;
431 u32 size = sizeof(gm20b_slcg_perf) / sizeof(struct gating_desc);
432
433 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
434 return;
435
436 for (i = 0; i < size; i++) {
437 if (prod)
438 gk20a_writel(g, gm20b_slcg_perf[i].addr,
439 gm20b_slcg_perf[i].prod);
440 else
441 gk20a_writel(g, gm20b_slcg_perf[i].addr,
442 gm20b_slcg_perf[i].disable);
443 }
444}
445
446void gm20b_slcg_priring_load_gating_prod(struct gk20a *g,
447 bool prod)
448{
449 u32 i;
450 u32 size = sizeof(gm20b_slcg_priring) / sizeof(struct gating_desc);
451
452 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
453 return;
454
455 for (i = 0; i < size; i++) {
456 if (prod)
457 gk20a_writel(g, gm20b_slcg_priring[i].addr,
458 gm20b_slcg_priring[i].prod);
459 else
460 gk20a_writel(g, gm20b_slcg_priring[i].addr,
461 gm20b_slcg_priring[i].disable);
462 }
463}
464
465void gm20b_slcg_pwr_csb_load_gating_prod(struct gk20a *g,
466 bool prod)
467{
468 u32 i;
469 u32 size = sizeof(gm20b_slcg_pwr_csb) / sizeof(struct gating_desc);
470
471 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
472 return;
473
474 for (i = 0; i < size; i++) {
475 if (prod)
476 gk20a_writel(g, gm20b_slcg_pwr_csb[i].addr,
477 gm20b_slcg_pwr_csb[i].prod);
478 else
479 gk20a_writel(g, gm20b_slcg_pwr_csb[i].addr,
480 gm20b_slcg_pwr_csb[i].disable);
481 }
482}
483
484void gm20b_slcg_pmu_load_gating_prod(struct gk20a *g,
485 bool prod)
486{
487 u32 i;
488 u32 size = sizeof(gm20b_slcg_pmu) / sizeof(struct gating_desc);
489
490 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
491 return;
492
493 for (i = 0; i < size; i++) {
494 if (prod)
495 gk20a_writel(g, gm20b_slcg_pmu[i].addr,
496 gm20b_slcg_pmu[i].prod);
497 else
498 gk20a_writel(g, gm20b_slcg_pmu[i].addr,
499 gm20b_slcg_pmu[i].disable);
500 }
501}
502
503void gm20b_slcg_therm_load_gating_prod(struct gk20a *g,
504 bool prod)
505{
506 u32 i;
507 u32 size = sizeof(gm20b_slcg_therm) / sizeof(struct gating_desc);
508
509 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
510 return;
511
512 for (i = 0; i < size; i++) {
513 if (prod)
514 gk20a_writel(g, gm20b_slcg_therm[i].addr,
515 gm20b_slcg_therm[i].prod);
516 else
517 gk20a_writel(g, gm20b_slcg_therm[i].addr,
518 gm20b_slcg_therm[i].disable);
519 }
520}
521
522void gm20b_slcg_xbar_load_gating_prod(struct gk20a *g,
523 bool prod)
524{
525 u32 i;
526 u32 size = sizeof(gm20b_slcg_xbar) / sizeof(struct gating_desc);
527
528 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
529 return;
530
531 for (i = 0; i < size; i++) {
532 if (prod)
533 gk20a_writel(g, gm20b_slcg_xbar[i].addr,
534 gm20b_slcg_xbar[i].prod);
535 else
536 gk20a_writel(g, gm20b_slcg_xbar[i].addr,
537 gm20b_slcg_xbar[i].disable);
538 }
539}
540
541void gm20b_blcg_bus_load_gating_prod(struct gk20a *g,
542 bool prod)
543{
544 u32 i;
545 u32 size = sizeof(gm20b_blcg_bus) / sizeof(struct gating_desc);
546
547 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
548 return;
549
550 for (i = 0; i < size; i++) {
551 if (prod)
552 gk20a_writel(g, gm20b_blcg_bus[i].addr,
553 gm20b_blcg_bus[i].prod);
554 else
555 gk20a_writel(g, gm20b_blcg_bus[i].addr,
556 gm20b_blcg_bus[i].disable);
557 }
558}
559
560void gm20b_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g,
561 bool prod)
562{
563 u32 i;
564 u32 size = sizeof(gm20b_blcg_ctxsw_prog) / sizeof(struct gating_desc);
565
566 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
567 return;
568
569 for (i = 0; i < size; i++) {
570 if (prod)
571 gk20a_writel(g, gm20b_blcg_ctxsw_prog[i].addr,
572 gm20b_blcg_ctxsw_prog[i].prod);
573 else
574 gk20a_writel(g, gm20b_blcg_ctxsw_prog[i].addr,
575 gm20b_blcg_ctxsw_prog[i].disable);
576 }
577}
578
579void gm20b_blcg_fb_load_gating_prod(struct gk20a *g,
580 bool prod)
581{
582 u32 i;
583 u32 size = sizeof(gm20b_blcg_fb) / sizeof(struct gating_desc);
584
585 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
586 return;
587
588 for (i = 0; i < size; i++) {
589 if (prod)
590 gk20a_writel(g, gm20b_blcg_fb[i].addr,
591 gm20b_blcg_fb[i].prod);
592 else
593 gk20a_writel(g, gm20b_blcg_fb[i].addr,
594 gm20b_blcg_fb[i].disable);
595 }
596}
597
598void gm20b_blcg_fifo_load_gating_prod(struct gk20a *g,
599 bool prod)
600{
601 u32 i;
602 u32 size = sizeof(gm20b_blcg_fifo) / sizeof(struct gating_desc);
603
604 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
605 return;
606
607 for (i = 0; i < size; i++) {
608 if (prod)
609 gk20a_writel(g, gm20b_blcg_fifo[i].addr,
610 gm20b_blcg_fifo[i].prod);
611 else
612 gk20a_writel(g, gm20b_blcg_fifo[i].addr,
613 gm20b_blcg_fifo[i].disable);
614 }
615}
616
617void gm20b_blcg_gr_load_gating_prod(struct gk20a *g,
618 bool prod)
619{
620 u32 i;
621 u32 size = sizeof(gm20b_blcg_gr) / sizeof(struct gating_desc);
622
623 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
624 return;
625
626 for (i = 0; i < size; i++) {
627 if (prod)
628 gk20a_writel(g, gm20b_blcg_gr[i].addr,
629 gm20b_blcg_gr[i].prod);
630 else
631 gk20a_writel(g, gm20b_blcg_gr[i].addr,
632 gm20b_blcg_gr[i].disable);
633 }
634}
635
636void gm20b_blcg_ltc_load_gating_prod(struct gk20a *g,
637 bool prod)
638{
639 u32 i;
640 u32 size = sizeof(gm20b_blcg_ltc) / sizeof(struct gating_desc);
641
642 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
643 return;
644
645 for (i = 0; i < size; i++) {
646 if (prod)
647 gk20a_writel(g, gm20b_blcg_ltc[i].addr,
648 gm20b_blcg_ltc[i].prod);
649 else
650 gk20a_writel(g, gm20b_blcg_ltc[i].addr,
651 gm20b_blcg_ltc[i].disable);
652 }
653}
654
655void gm20b_blcg_pwr_csb_load_gating_prod(struct gk20a *g,
656 bool prod)
657{
658 u32 i;
659 u32 size = sizeof(gm20b_blcg_pwr_csb) / sizeof(struct gating_desc);
660
661 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
662 return;
663
664 for (i = 0; i < size; i++) {
665 if (prod)
666 gk20a_writel(g, gm20b_blcg_pwr_csb[i].addr,
667 gm20b_blcg_pwr_csb[i].prod);
668 else
669 gk20a_writel(g, gm20b_blcg_pwr_csb[i].addr,
670 gm20b_blcg_pwr_csb[i].disable);
671 }
672}
673
674void gm20b_blcg_pmu_load_gating_prod(struct gk20a *g,
675 bool prod)
676{
677 u32 i;
678 u32 size = sizeof(gm20b_blcg_pmu) / sizeof(struct gating_desc);
679
680 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
681 return;
682
683 for (i = 0; i < size; i++) {
684 if (prod)
685 gk20a_writel(g, gm20b_blcg_pmu[i].addr,
686 gm20b_blcg_pmu[i].prod);
687 else
688 gk20a_writel(g, gm20b_blcg_pmu[i].addr,
689 gm20b_blcg_pmu[i].disable);
690 }
691}
692
693void gm20b_blcg_xbar_load_gating_prod(struct gk20a *g,
694 bool prod)
695{
696 u32 i;
697 u32 size = sizeof(gm20b_blcg_xbar) / sizeof(struct gating_desc);
698
699 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
700 return;
701
702 for (i = 0; i < size; i++) {
703 if (prod)
704 gk20a_writel(g, gm20b_blcg_xbar[i].addr,
705 gm20b_blcg_xbar[i].prod);
706 else
707 gk20a_writel(g, gm20b_blcg_xbar[i].addr,
708 gm20b_blcg_xbar[i].disable);
709 }
710}
711
712void gr_gm20b_pg_gr_load_gating_prod(struct gk20a *g,
713 bool prod)
714{
715 u32 i;
716 u32 size = sizeof(gm20b_pg_gr) / sizeof(struct gating_desc);
717
718 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
719 return;
720
721 for (i = 0; i < size; i++) {
722 if (prod)
723 gk20a_writel(g, gm20b_pg_gr[i].addr,
724 gm20b_pg_gr[i].prod);
725 else
726 gk20a_writel(g, gm20b_pg_gr[i].addr,
727 gm20b_pg_gr[i].disable);
728 }
729}
730
731#endif /* __gm20b_gating_reglist_h__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-04 21:25:38 -0400