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authorsmadhavan <smadhavan@nvidia.com>2018-09-05 03:18:10 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-09-06 19:13:08 -0400
commit5cfd481cf5319d52f613cb5c5f66a1f643af5bed (patch)
tree7cb3ba23eb7c9e652b027898b76d8e90570d00bd /drivers/gpu/nvgpu/gm20b/fifo_gm20b.h
parent935f05b741b1b8470862f5326affa0bea60263cb (diff)
nvgpu: gm20b: MISRA Rule 21.2 header gurad fixes
MISRA rule 21.2 doesn't allow the use of macro names which start with an underscore. These leading underscores are to be removed from the macro names. This patch will fix such violations caused by include guards by renaming them to follow the convention, 'NVGPU_PARENT-DIR_HEADER_H' JIRA NVGPU-1028 Change-Id: Ic60b2de8bb705f189134483fff1e2dff8ea96a12 Signed-off-by: smadhavan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1808186 GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/fifo_gm20b.h')
-rw-r--r--drivers/gpu/nvgpu/gm20b/fifo_gm20b.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.h b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.h
index f9e1f95d..b9e20721 100644
--- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.h
@@ -22,8 +22,8 @@
22 * DEALINGS IN THE SOFTWARE. 22 * DEALINGS IN THE SOFTWARE.
23 */ 23 */
24 24
25#ifndef _NVHOST_GM20B_FIFO 25#ifndef NVGPU_GM20B_FIFO_GM20B_H
26#define _NVHOST_GM20B_FIFO 26#define NVGPU_GM20B_FIFO_GM20B_H
27struct gk20a; 27struct gk20a;
28struct mmu_fault_info; 28struct mmu_fault_info;
29 29
@@ -38,4 +38,4 @@ void gm20b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f);
38void gm20b_fifo_tsg_verify_status_ctx_reload(struct channel_gk20a *ch); 38void gm20b_fifo_tsg_verify_status_ctx_reload(struct channel_gk20a *ch);
39void gm20b_fifo_get_mmu_fault_gpc_desc(struct mmu_fault_info *mmfault); 39void gm20b_fifo_get_mmu_fault_gpc_desc(struct mmu_fault_info *mmfault);
40 40
41#endif 41#endif /* NVGPU_GM20B_FIFO_GM20B_H */