summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
diff options
context:
space:
mode:
authorLakshmanan M <lm@nvidia.com>2016-05-23 02:50:14 -0400
committerTerje Bergstrom <tbergstrom@nvidia.com>2016-05-27 14:36:52 -0400
commitf3cb140a71f179ce023bac48d5b92537893214a1 (patch)
tree597639f2003949c53b0c15f0bd6c8e56be23838f /drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
parent20c65d8f4a6cca705472bbdde52bd2fce3c6e274 (diff)
gpu: nvgpu: Add device_info_data support
Added device_info_data parsing support for maxwell GPU series. JIRA DNVGPU-26 Change-Id: I06dbec6056d4c26501e607c2c3d67ef468d206f4 Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1151602 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/fifo_gm20b.c')
-rw-r--r--drivers/gpu/nvgpu/gm20b/fifo_gm20b.c46
1 files changed, 35 insertions, 11 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
index a6d953a4..eaa22dc2 100644
--- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
@@ -19,6 +19,7 @@
19#include "hw_ccsr_gm20b.h" 19#include "hw_ccsr_gm20b.h"
20#include "hw_ram_gm20b.h" 20#include "hw_ram_gm20b.h"
21#include "hw_fifo_gm20b.h" 21#include "hw_fifo_gm20b.h"
22#include "hw_top_gm20b.h"
22 23
23static void channel_gm20b_bind(struct channel_gk20a *c) 24static void channel_gm20b_bind(struct channel_gk20a *c)
24{ 25{
@@ -45,16 +46,17 @@ static void channel_gm20b_bind(struct channel_gk20a *c)
45 ccsr_channel_enable_set_true_f()); 46 ccsr_channel_enable_set_true_f());
46} 47}
47 48
48static inline u32 gm20b_engine_id_to_mmu_id(u32 engine_id) 49static inline u32 gm20b_engine_id_to_mmu_id(struct gk20a *g, u32 engine_id)
49{ 50{
50 switch (engine_id) { 51 u32 fault_id = ~0;
51 case ENGINE_GR_GK20A: 52
52 return 0; 53 if (engine_id < ENGINE_INVAL_GK20A) {
53 case ENGINE_CE2_GK20A: 54 struct fifo_engine_info_gk20a *info =
54 return 1; 55 &g->fifo.engine_info[engine_id];
55 default: 56
56 return ~0; 57 fault_id = info->fault_id;
57 } 58 }
59 return fault_id;
58} 60}
59 61
60static void gm20b_fifo_trigger_mmu_fault(struct gk20a *g, 62static void gm20b_fifo_trigger_mmu_fault(struct gk20a *g,
@@ -68,14 +70,15 @@ static void gm20b_fifo_trigger_mmu_fault(struct gk20a *g,
68 70
69 /* trigger faults for all bad engines */ 71 /* trigger faults for all bad engines */
70 for_each_set_bit(engine_id, &engine_ids, 32) { 72 for_each_set_bit(engine_id, &engine_ids, 32) {
71 u32 engine_mmu_id; 73 u32 engine_mmu_fault_id;
72 74
73 if (engine_id > g->fifo.max_engines) { 75 if (engine_id > g->fifo.max_engines) {
74 gk20a_err(dev_from_gk20a(g), 76 gk20a_err(dev_from_gk20a(g),
75 "faulting unknown engine %ld", engine_id); 77 "faulting unknown engine %ld", engine_id);
76 } else { 78 } else {
77 engine_mmu_id = gm20b_engine_id_to_mmu_id(engine_id); 79 engine_mmu_fault_id = gm20b_engine_id_to_mmu_id(g,
78 gk20a_writel(g, fifo_trigger_mmu_fault_r(engine_mmu_id), 80 engine_id);
81 gk20a_writel(g, fifo_trigger_mmu_fault_r(engine_id),
79 fifo_trigger_mmu_fault_enable_f(1)); 82 fifo_trigger_mmu_fault_enable_f(1));
80 } 83 }
81 } 84 }
@@ -106,6 +109,26 @@ static u32 gm20b_fifo_get_num_fifos(struct gk20a *g)
106 return ccsr_channel__size_1_v(); 109 return ccsr_channel__size_1_v();
107} 110}
108 111
112void gm20b_device_info_data_parse(struct gk20a *g,
113 u32 table_entry, u32 *inst_id,
114 u32 *pri_base, u32 *fault_id)
115{
116 if (top_device_info_data_type_v(table_entry) ==
117 top_device_info_data_type_enum2_v()) {
118 if (pri_base) {
119 *pri_base =
120 (top_device_info_data_pri_base_v(table_entry)
121 << top_device_info_data_pri_base_align_v());
122 }
123 if (fault_id && (top_device_info_data_fault_id_v(table_entry) ==
124 top_device_info_data_fault_id_valid_v())) {
125 *fault_id =
126 top_device_info_data_fault_id_enum_v(table_entry);
127 }
128 } else
129 gk20a_err(g->dev, "unknown device_info_data %d",
130 top_device_info_data_type_v(table_entry));
131}
109void gm20b_init_fifo(struct gpu_ops *gops) 132void gm20b_init_fifo(struct gpu_ops *gops)
110{ 133{
111 gops->fifo.bind_channel = channel_gm20b_bind; 134 gops->fifo.bind_channel = channel_gm20b_bind;
@@ -127,4 +150,5 @@ void gm20b_init_fifo(struct gpu_ops *gops)
127 gops->fifo.set_runlist_interleave = gk20a_fifo_set_runlist_interleave; 150 gops->fifo.set_runlist_interleave = gk20a_fifo_set_runlist_interleave;
128 gops->fifo.force_reset_ch = gk20a_fifo_force_reset_ch; 151 gops->fifo.force_reset_ch = gk20a_fifo_force_reset_ch;
129 gops->fifo.engine_enum_from_type = gk20a_fifo_engine_enum_from_type; 152 gops->fifo.engine_enum_from_type = gk20a_fifo_engine_enum_from_type;
153 gops->fifo.device_info_data_parse = gm20b_device_info_data_parse;
130} 154}