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authorTerje Bergstrom <tbergstrom@nvidia.com>2017-04-06 14:01:46 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-04-07 16:48:18 -0400
commitbb72b7e2ed215b26e1d9b94534c24ab4cfa52801 (patch)
tree2a8e781838616f4640d7ef3e5c04ae7d996e0ecf /drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
parent85f27cec5d010d4ac0f4646f11f145d4b3a122e4 (diff)
gpu: nvgpu: gm20b: Use new error macros
gk20a_err() and gk20a_warn() require a struct device pointer, which is not portable across operating systems. The new nvgpu_err() and nvgpu_warn() macros take struct gk20a pointer. Convert code to use the more portable macros. JIRA NVGPU-16 Change-Id: Ic27fb98e03a982e5a1cf672cb4e8f87ecea10a5b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1457345 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/fifo_gm20b.c')
-rw-r--r--drivers/gpu/nvgpu/gm20b/fifo_gm20b.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
index 6c34689b..e3aa43d6 100644
--- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
@@ -21,6 +21,7 @@
21#include "fifo_gm20b.h" 21#include "fifo_gm20b.h"
22 22
23#include <nvgpu/timers.h> 23#include <nvgpu/timers.h>
24#include <nvgpu/log.h>
24 25
25#include <nvgpu/hw/gm20b/hw_ccsr_gm20b.h> 26#include <nvgpu/hw/gm20b/hw_ccsr_gm20b.h>
26#include <nvgpu/hw/gm20b/hw_ram_gm20b.h> 27#include <nvgpu/hw/gm20b/hw_ram_gm20b.h>
@@ -64,7 +65,7 @@ static inline u32 gm20b_engine_id_to_mmu_id(struct gk20a *g, u32 engine_id)
64 if (engine_info) { 65 if (engine_info) {
65 fault_id = engine_info->fault_id; 66 fault_id = engine_info->fault_id;
66 } else { 67 } else {
67 gk20a_err(g->dev, "engine_id is not in active list/invalid %d", engine_id); 68 nvgpu_err(g, "engine_id is not in active list/invalid %d", engine_id);
68 } 69 }
69 return fault_id; 70 return fault_id;
70} 71}
@@ -80,8 +81,7 @@ static void gm20b_fifo_trigger_mmu_fault(struct gk20a *g,
80 /* trigger faults for all bad engines */ 81 /* trigger faults for all bad engines */
81 for_each_set_bit(engine_id, &engine_ids, 32) { 82 for_each_set_bit(engine_id, &engine_ids, 32) {
82 if (!gk20a_fifo_is_valid_engine_id(g, engine_id)) { 83 if (!gk20a_fifo_is_valid_engine_id(g, engine_id)) {
83 gk20a_err(dev_from_gk20a(g), 84 nvgpu_err(g, "faulting unknown engine %ld", engine_id);
84 "faulting unknown engine %ld", engine_id);
85 } else { 85 } else {
86 u32 mmu_id = gm20b_engine_id_to_mmu_id(g, 86 u32 mmu_id = gm20b_engine_id_to_mmu_id(g,
87 engine_id); 87 engine_id);
@@ -107,7 +107,7 @@ static void gm20b_fifo_trigger_mmu_fault(struct gk20a *g,
107 } while (!nvgpu_timeout_expired(&timeout)); 107 } while (!nvgpu_timeout_expired(&timeout));
108 108
109 if (ret) 109 if (ret)
110 gk20a_err(dev_from_gk20a(g), "mmu fault timeout"); 110 nvgpu_err(g, "mmu fault timeout");
111 111
112 /* release mmu fault trigger */ 112 /* release mmu fault trigger */
113 for_each_set_bit(engine_id, &engine_ids, 32) 113 for_each_set_bit(engine_id, &engine_ids, 32)
@@ -136,7 +136,7 @@ static void gm20b_device_info_data_parse(struct gk20a *g,
136 top_device_info_data_fault_id_enum_v(table_entry); 136 top_device_info_data_fault_id_enum_v(table_entry);
137 } 137 }
138 } else 138 } else
139 gk20a_err(g->dev, "unknown device_info_data %d", 139 nvgpu_err(g, "unknown device_info_data %d",
140 top_device_info_data_type_v(table_entry)); 140 top_device_info_data_type_v(table_entry));
141} 141}
142 142