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authorSunny He <suhe@nvidia.com>2017-06-30 18:53:08 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-07-24 02:35:06 -0400
commit66ec347db401affd8bcd425dc123e7162b9ae3bb (patch)
treecbeb24e465208c6ab3b9527a86ba35003837f176 /drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
parent2b582c5141752ff272c5d059b56433155bc3985a (diff)
gpu: nvgpu: Reorg fifo HAL initialization
Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the fifo sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I43d94067a1d7eafba4cdb28311e0ce25812013a7 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1522553 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/fifo_gm20b.c')
-rw-r--r--drivers/gpu/nvgpu/gm20b/fifo_gm20b.c71
1 files changed, 5 insertions, 66 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
index 19782412..afdfba91 100644
--- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
@@ -28,7 +28,7 @@
28#include <nvgpu/hw/gm20b/hw_top_gm20b.h> 28#include <nvgpu/hw/gm20b/hw_top_gm20b.h>
29#include <nvgpu/hw/gm20b/hw_pbdma_gm20b.h> 29#include <nvgpu/hw/gm20b/hw_pbdma_gm20b.h>
30 30
31static void channel_gm20b_bind(struct channel_gk20a *c) 31void channel_gm20b_bind(struct channel_gk20a *c)
32{ 32{
33 struct gk20a *g = c->g; 33 struct gk20a *g = c->g;
34 34
@@ -69,7 +69,7 @@ static inline u32 gm20b_engine_id_to_mmu_id(struct gk20a *g, u32 engine_id)
69 return fault_id; 69 return fault_id;
70} 70}
71 71
72static void gm20b_fifo_trigger_mmu_fault(struct gk20a *g, 72void gm20b_fifo_trigger_mmu_fault(struct gk20a *g,
73 unsigned long engine_ids) 73 unsigned long engine_ids)
74{ 74{
75 unsigned long delay = GR_IDLE_CHECK_DEFAULT; 75 unsigned long delay = GR_IDLE_CHECK_DEFAULT;
@@ -113,12 +113,12 @@ static void gm20b_fifo_trigger_mmu_fault(struct gk20a *g,
113 gk20a_writel(g, fifo_trigger_mmu_fault_r(engine_id), 0); 113 gk20a_writel(g, fifo_trigger_mmu_fault_r(engine_id), 0);
114} 114}
115 115
116static u32 gm20b_fifo_get_num_fifos(struct gk20a *g) 116u32 gm20b_fifo_get_num_fifos(struct gk20a *g)
117{ 117{
118 return ccsr_channel__size_1_v(); 118 return ccsr_channel__size_1_v();
119} 119}
120 120
121static void gm20b_device_info_data_parse(struct gk20a *g, 121void gm20b_device_info_data_parse(struct gk20a *g,
122 u32 table_entry, u32 *inst_id, 122 u32 table_entry, u32 *inst_id,
123 u32 *pri_base, u32 *fault_id) 123 u32 *pri_base, u32 *fault_id)
124{ 124{
@@ -139,7 +139,7 @@ static void gm20b_device_info_data_parse(struct gk20a *g,
139 top_device_info_data_type_v(table_entry)); 139 top_device_info_data_type_v(table_entry));
140} 140}
141 141
142static void gm20b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f) 142void gm20b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f)
143{ 143{
144 /* 144 /*
145 * These are all errors which indicate something really wrong 145 * These are all errors which indicate something really wrong
@@ -182,64 +182,3 @@ static void gm20b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f)
182 f->intr.pbdma.restartable_0 = 182 f->intr.pbdma.restartable_0 =
183 pbdma_intr_0_device_pending_f(); 183 pbdma_intr_0_device_pending_f();
184} 184}
185
186void gm20b_init_fifo(struct gpu_ops *gops)
187{
188 gops->fifo.init_fifo_setup_hw = gk20a_init_fifo_setup_hw;
189 gops->fifo.bind_channel = channel_gm20b_bind;
190 gops->fifo.unbind_channel = gk20a_fifo_channel_unbind;
191 gops->fifo.disable_channel = gk20a_fifo_disable_channel;
192 gops->fifo.enable_channel = gk20a_fifo_enable_channel;
193 gops->fifo.alloc_inst = gk20a_fifo_alloc_inst;
194 gops->fifo.free_inst = gk20a_fifo_free_inst;
195 gops->fifo.setup_ramfc = gk20a_fifo_setup_ramfc;
196 gops->fifo.channel_set_priority = gk20a_fifo_set_priority;
197 gops->fifo.channel_set_timeslice = gk20a_fifo_set_timeslice;
198 gops->fifo.default_timeslice_us = gk20a_fifo_default_timeslice_us;
199 gops->fifo.setup_userd = gk20a_fifo_setup_userd;
200 gops->fifo.userd_gp_get = gk20a_fifo_userd_gp_get;
201 gops->fifo.userd_gp_put = gk20a_fifo_userd_gp_put;
202 gops->fifo.userd_pb_get = gk20a_fifo_userd_pb_get;
203 gops->fifo.pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val;
204
205 gops->fifo.preempt_channel = gk20a_fifo_preempt_channel;
206 gops->fifo.preempt_tsg = gk20a_fifo_preempt_tsg;
207 gops->fifo.update_runlist = gk20a_fifo_update_runlist;
208 gops->fifo.trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault;
209 gops->fifo.get_mmu_fault_info = gk20a_fifo_get_mmu_fault_info;
210 gops->fifo.wait_engine_idle = gk20a_fifo_wait_engine_idle;
211 gops->fifo.get_num_fifos = gm20b_fifo_get_num_fifos;
212 gops->fifo.get_pbdma_signature = gk20a_fifo_get_pbdma_signature;
213 gops->fifo.set_runlist_interleave = gk20a_fifo_set_runlist_interleave;
214 gops->fifo.tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice;
215 gops->fifo.force_reset_ch = gk20a_fifo_force_reset_ch;
216 gops->fifo.engine_enum_from_type = gk20a_fifo_engine_enum_from_type;
217 gops->fifo.device_info_data_parse = gm20b_device_info_data_parse;
218 gops->fifo.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v;
219 gops->fifo.init_engine_info = gk20a_fifo_init_engine_info;
220 gops->fifo.runlist_entry_size = ram_rl_entry_size_v;
221 gops->fifo.get_tsg_runlist_entry = gk20a_get_tsg_runlist_entry;
222 gops->fifo.get_ch_runlist_entry = gk20a_get_ch_runlist_entry;
223 gops->fifo.is_fault_engine_subid_gpc = gk20a_is_fault_engine_subid_gpc;
224 gops->fifo.dump_pbdma_status = gk20a_dump_pbdma_status;
225 gops->fifo.dump_eng_status = gk20a_dump_eng_status;
226 gops->fifo.dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc;
227 gops->fifo.intr_0_error_mask = gk20a_fifo_intr_0_error_mask;
228 gops->fifo.is_preempt_pending = gk20a_fifo_is_preempt_pending;
229 gops->fifo.init_pbdma_intr_descs = gm20b_fifo_init_pbdma_intr_descs;
230 gops->fifo.reset_enable_hw = gk20a_init_fifo_reset_enable_hw;
231 gops->fifo.teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg;
232 gops->fifo.handle_sched_error = gk20a_fifo_handle_sched_error;
233 gops->fifo.handle_pbdma_intr_0 = gk20a_fifo_handle_pbdma_intr_0;
234 gops->fifo.handle_pbdma_intr_1 = gk20a_fifo_handle_pbdma_intr_1;
235#ifdef CONFIG_TEGRA_GK20A_NVHOST
236 gops->fifo.alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf;
237 gops->fifo.free_syncpt_buf = gk20a_fifo_free_syncpt_buf;
238 gops->fifo.add_syncpt_wait_cmd = gk20a_fifo_add_syncpt_wait_cmd;
239 gops->fifo.get_syncpt_wait_cmd_size =
240 gk20a_fifo_get_syncpt_wait_cmd_size;
241 gops->fifo.add_syncpt_incr_cmd = gk20a_fifo_add_syncpt_incr_cmd;
242 gops->fifo.get_syncpt_incr_cmd_size =
243 gk20a_fifo_get_syncpt_incr_cmd_size;
244#endif
245}