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authorTerje Bergstrom <tbergstrom@nvidia.com>2018-07-02 17:30:26 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-07-12 23:44:13 -0400
commitb97bcb3c689426a1b099e88ceef4d55584e2362b (patch)
tree4ad683912a323eca81a493314db3d74b46b6aa71 /drivers/gpu/nvgpu/gm20b/fb_gm20b.c
parentb07a304ba3e747c80fe3e0a16caec88c8e1e8b28 (diff)
gpu: nvgpu: Move FB to common
Move all FB HAL implementations to common/fb. JIRA NVGPU-596 Change-Id: Id4ea09d608f5d6d1b245bddac09ecf1444b8ab30 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1769724 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/fb_gm20b.c')
-rw-r--r--drivers/gpu/nvgpu/gm20b/fb_gm20b.c228
1 files changed, 0 insertions, 228 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/fb_gm20b.c b/drivers/gpu/nvgpu/gm20b/fb_gm20b.c
deleted file mode 100644
index 37a7944b..00000000
--- a/drivers/gpu/nvgpu/gm20b/fb_gm20b.c
+++ /dev/null
@@ -1,228 +0,0 @@
1/*
2 * GM20B GPC MMU
3 *
4 * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
5*
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#include <nvgpu/sizes.h>
26
27#include "gk20a/gk20a.h"
28#include "gk20a/fb_gk20a.h"
29#include "gm20b/fb_gm20b.h"
30
31#include <nvgpu/hw/gm20b/hw_fb_gm20b.h>
32#include <nvgpu/hw/gm20b/hw_top_gm20b.h>
33#include <nvgpu/hw/gm20b/hw_gmmu_gm20b.h>
34#include <nvgpu/hw/gm20b/hw_gr_gm20b.h>
35
36#define VPR_INFO_FETCH_WAIT (5)
37#define WPR_INFO_ADDR_ALIGNMENT 0x0000000c
38
39void fb_gm20b_init_fs_state(struct gk20a *g)
40{
41 nvgpu_log_info(g, "initialize gm20b fb");
42
43 gk20a_writel(g, fb_fbhub_num_active_ltcs_r(),
44 g->ltc_count);
45
46 if (!nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
47 /* Bypass MMU check for non-secure boot. For
48 * secure-boot,this register write has no-effect */
49 gk20a_writel(g, fb_priv_mmu_phy_secure_r(), 0xffffffffU);
50 }
51}
52
53void gm20b_fb_set_mmu_page_size(struct gk20a *g)
54{
55 /* set large page size in fb */
56 u32 fb_mmu_ctrl = gk20a_readl(g, fb_mmu_ctrl_r());
57 fb_mmu_ctrl |= fb_mmu_ctrl_use_pdb_big_page_size_true_f();
58 gk20a_writel(g, fb_mmu_ctrl_r(), fb_mmu_ctrl);
59}
60
61bool gm20b_fb_set_use_full_comp_tag_line(struct gk20a *g)
62{
63 /* set large page size in fb */
64 u32 fb_mmu_ctrl = gk20a_readl(g, fb_mmu_ctrl_r());
65 fb_mmu_ctrl |= fb_mmu_ctrl_use_full_comp_tag_line_true_f();
66 gk20a_writel(g, fb_mmu_ctrl_r(), fb_mmu_ctrl);
67
68 return true;
69}
70
71u32 gm20b_fb_mmu_ctrl(struct gk20a *g)
72{
73 return gk20a_readl(g, fb_mmu_ctrl_r());
74}
75
76u32 gm20b_fb_mmu_debug_ctrl(struct gk20a *g)
77{
78 return gk20a_readl(g, fb_mmu_debug_ctrl_r());
79}
80
81u32 gm20b_fb_mmu_debug_wr(struct gk20a *g)
82{
83 return gk20a_readl(g, fb_mmu_debug_wr_r());
84}
85
86u32 gm20b_fb_mmu_debug_rd(struct gk20a *g)
87{
88 return gk20a_readl(g, fb_mmu_debug_rd_r());
89}
90
91unsigned int gm20b_fb_compression_page_size(struct gk20a *g)
92{
93 return SZ_128K;
94}
95
96unsigned int gm20b_fb_compressible_page_size(struct gk20a *g)
97{
98 return SZ_64K;
99}
100
101u32 gm20b_fb_compression_align_mask(struct gk20a *g)
102{
103 return SZ_64K - 1;
104}
105
106void gm20b_fb_dump_vpr_wpr_info(struct gk20a *g)
107{
108 u32 val;
109
110 /* print vpr and wpr info */
111 val = gk20a_readl(g, fb_mmu_vpr_info_r());
112 val &= ~0x3;
113 val |= fb_mmu_vpr_info_index_addr_lo_v();
114 gk20a_writel(g, fb_mmu_vpr_info_r(), val);
115 nvgpu_err(g, "VPR: %08x %08x %08x %08x",
116 gk20a_readl(g, fb_mmu_vpr_info_r()),
117 gk20a_readl(g, fb_mmu_vpr_info_r()),
118 gk20a_readl(g, fb_mmu_vpr_info_r()),
119 gk20a_readl(g, fb_mmu_vpr_info_r()));
120
121 val = gk20a_readl(g, fb_mmu_wpr_info_r());
122 val &= ~0xf;
123 val |= (fb_mmu_wpr_info_index_allow_read_v());
124 gk20a_writel(g, fb_mmu_wpr_info_r(), val);
125 nvgpu_err(g, "WPR: %08x %08x %08x %08x %08x %08x",
126 gk20a_readl(g, fb_mmu_wpr_info_r()),
127 gk20a_readl(g, fb_mmu_wpr_info_r()),
128 gk20a_readl(g, fb_mmu_wpr_info_r()),
129 gk20a_readl(g, fb_mmu_wpr_info_r()),
130 gk20a_readl(g, fb_mmu_wpr_info_r()),
131 gk20a_readl(g, fb_mmu_wpr_info_r()));
132
133}
134
135static int gm20b_fb_vpr_info_fetch_wait(struct gk20a *g,
136 unsigned int msec)
137{
138 struct nvgpu_timeout timeout;
139
140 nvgpu_timeout_init(g, &timeout, msec, NVGPU_TIMER_CPU_TIMER);
141
142 do {
143 u32 val;
144
145 val = gk20a_readl(g, fb_mmu_vpr_info_r());
146 if (fb_mmu_vpr_info_fetch_v(val) ==
147 fb_mmu_vpr_info_fetch_false_v())
148 return 0;
149
150 } while (!nvgpu_timeout_expired(&timeout));
151
152 return -ETIMEDOUT;
153}
154
155int gm20b_fb_vpr_info_fetch(struct gk20a *g)
156{
157 if (gm20b_fb_vpr_info_fetch_wait(g, VPR_INFO_FETCH_WAIT)) {
158 return -ETIMEDOUT;
159 }
160
161 gk20a_writel(g, fb_mmu_vpr_info_r(),
162 fb_mmu_vpr_info_fetch_true_v());
163
164 return gm20b_fb_vpr_info_fetch_wait(g, VPR_INFO_FETCH_WAIT);
165}
166
167void gm20b_fb_read_wpr_info(struct gk20a *g, struct wpr_carveout_info *inf)
168{
169 u32 val = 0;
170 u64 wpr_start = 0;
171 u64 wpr_end = 0;
172
173 val = gk20a_readl(g, fb_mmu_wpr_info_r());
174 val &= ~0xF;
175 val |= fb_mmu_wpr_info_index_wpr1_addr_lo_v();
176 gk20a_writel(g, fb_mmu_wpr_info_r(), val);
177
178 val = gk20a_readl(g, fb_mmu_wpr_info_r()) >> 0x4;
179 wpr_start = hi32_lo32_to_u64(
180 (val >> (32 - WPR_INFO_ADDR_ALIGNMENT)),
181 (val << WPR_INFO_ADDR_ALIGNMENT));
182
183 val = gk20a_readl(g, fb_mmu_wpr_info_r());
184 val &= ~0xF;
185 val |= fb_mmu_wpr_info_index_wpr1_addr_hi_v();
186 gk20a_writel(g, fb_mmu_wpr_info_r(), val);
187
188 val = gk20a_readl(g, fb_mmu_wpr_info_r()) >> 0x4;
189 wpr_end = hi32_lo32_to_u64(
190 (val >> (32 - WPR_INFO_ADDR_ALIGNMENT)),
191 (val << WPR_INFO_ADDR_ALIGNMENT));
192
193 inf->wpr_base = wpr_start;
194 inf->nonwpr_base = 0;
195 inf->size = (wpr_end - wpr_start);
196}
197
198bool gm20b_fb_debug_mode_enabled(struct gk20a *g)
199{
200 u32 debug_ctrl = gk20a_readl(g, gr_gpcs_pri_mmu_debug_ctrl_r());
201 return gr_gpcs_pri_mmu_debug_ctrl_debug_v(debug_ctrl) ==
202 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v();
203}
204
205void gm20b_fb_set_debug_mode(struct gk20a *g, bool enable)
206{
207 u32 reg_val, fb_debug_ctrl, gpc_debug_ctrl;
208
209 if (enable) {
210 fb_debug_ctrl = fb_mmu_debug_ctrl_debug_enabled_f();
211 gpc_debug_ctrl = gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_f();
212 g->mmu_debug_ctrl = true;
213 } else {
214 fb_debug_ctrl = fb_mmu_debug_ctrl_debug_disabled_f();
215 gpc_debug_ctrl = gr_gpcs_pri_mmu_debug_ctrl_debug_disabled_f();
216 g->mmu_debug_ctrl = false;
217 }
218
219 reg_val = gk20a_readl(g, fb_mmu_debug_ctrl_r());
220 reg_val = set_field(reg_val,
221 fb_mmu_debug_ctrl_debug_m(), fb_debug_ctrl);
222 gk20a_writel(g, fb_mmu_debug_ctrl_r(), reg_val);
223
224 reg_val = gk20a_readl(g, gr_gpcs_pri_mmu_debug_ctrl_r());
225 reg_val = set_field(reg_val,
226 gr_gpcs_pri_mmu_debug_ctrl_debug_m(), gpc_debug_ctrl);
227 gk20a_writel(g, gr_gpcs_pri_mmu_debug_ctrl_r(), reg_val);
228}
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