diff options
author | Sunny He <suhe@nvidia.com> | 2017-06-29 17:24:29 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-08-02 17:43:27 -0400 |
commit | 11e29991acd25baef5b786605e136b5e71737b8e (patch) | |
tree | 1fd738a07e172ef7cdc2882359424be246964ce3 /drivers/gpu/nvgpu/gm20b/clk_gm20b.h | |
parent | a15e110a9b790f55a5c6e257cfbf7f7235f5a334 (diff) |
gpu: nvgpu: Reorg clk HAL initialization
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the clk
and clk_arb sub-module of the gpu_ops struct.
Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.
Jira NVGPU-74
Change-Id: I553353df836b187b8eac61e16b63080b570c96b8
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1511076
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/clk_gm20b.h')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/clk_gm20b.h | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.h b/drivers/gpu/nvgpu/gm20b/clk_gm20b.h index 1e06d651..07e0d04d 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.h | |||
@@ -50,8 +50,6 @@ struct nvgpu_clk_pll_debug_data { | |||
50 | u32 trim_sys_gpcpll_dvfs0_dfs_dc_offset; | 50 | u32 trim_sys_gpcpll_dvfs0_dfs_dc_offset; |
51 | }; | 51 | }; |
52 | 52 | ||
53 | void gm20b_init_clk_ops(struct gpu_ops *gops); | ||
54 | |||
55 | int gm20b_init_clk_setup_sw(struct gk20a *g); | 53 | int gm20b_init_clk_setup_sw(struct gk20a *g); |
56 | 54 | ||
57 | int gm20b_clk_prepare(struct clk_gk20a *clk); | 55 | int gm20b_clk_prepare(struct clk_gk20a *clk); |
@@ -67,6 +65,14 @@ struct pll_parms *gm20b_get_gpc_pll_parms(void); | |||
67 | int gm20b_clk_init_debugfs(struct gk20a *g); | 65 | int gm20b_clk_init_debugfs(struct gk20a *g); |
68 | #endif | 66 | #endif |
69 | 67 | ||
68 | int gm20b_clk_pll_reg_write(struct gk20a *g, u32 reg, u32 val); | ||
69 | int gm20b_init_clk_support(struct gk20a *g); | ||
70 | int gm20b_suspend_clk_support(struct gk20a *g); | ||
71 | int gm20b_clk_get_voltage(struct clk_gk20a *clk, u64 *val); | ||
72 | int gm20b_clk_get_gpcclk_clock_counter(struct clk_gk20a *clk, u64 *val); | ||
73 | int gm20b_clk_get_pll_debug_data(struct gk20a *g, | ||
74 | struct nvgpu_clk_pll_debug_data *d); | ||
75 | |||
70 | /* 1:1 match between post divider settings and divisor value */ | 76 | /* 1:1 match between post divider settings and divisor value */ |
71 | static inline u32 nvgpu_pl_to_div(u32 pl) | 77 | static inline u32 nvgpu_pl_to_div(u32 pl) |
72 | { | 78 | { |