diff options
author | Deepak Nibade <dnibade@nvidia.com> | 2017-05-22 02:49:38 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-05-24 07:55:53 -0400 |
commit | c32aa0170d258f6db5252cc319a58b626bd8f7e0 (patch) | |
tree | 54a643057c5e87c492630af172b3cccb21e1116c /drivers/gpu/nvgpu/gm20b/clk_gm20b.c | |
parent | ec964208c14e29ea46ea22f44a3ae718f36e17fa (diff) |
gpu: nvgpu: remove clk_common.c
clk/clk_common.c includes some linux specific clock
calls which can be easily replaced
Move linux specific call to platform file
Rest of the APIs are removed by directly substituting
API code into caller function
Jira NVGPU-49
Change-Id: Ia70e7a65c877649699b5d064683c34c0cb696d2e
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1483862
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/clk_gm20b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/clk_gm20b.c | 11 |
1 files changed, 4 insertions, 7 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c index c4e65767..3d90938d 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c | |||
@@ -1147,11 +1147,6 @@ int gm20b_init_clk_setup_sw(struct gk20a *g) | |||
1147 | clk->pll_poweron_uv = BOOT_GPU_UV_B1; | 1147 | clk->pll_poweron_uv = BOOT_GPU_UV_B1; |
1148 | } | 1148 | } |
1149 | 1149 | ||
1150 | if (!gk20a_clk_get(g)) { | ||
1151 | err = -EINVAL; | ||
1152 | goto fail; | ||
1153 | } | ||
1154 | |||
1155 | clk->gpc_pll.clk_in = g->ops.clk.get_ref_clock_rate(g) / KHZ; | 1150 | clk->gpc_pll.clk_in = g->ops.clk.get_ref_clock_rate(g) / KHZ; |
1156 | if (clk->gpc_pll.clk_in == 0) { | 1151 | if (clk->gpc_pll.clk_in == 0) { |
1157 | nvgpu_err(g, "GPCPLL reference clock is zero"); | 1152 | nvgpu_err(g, "GPCPLL reference clock is zero"); |
@@ -1451,13 +1446,15 @@ void gm20b_init_clk_ops(struct gpu_ops *gops) | |||
1451 | static int rate_get(void *data, u64 *val) | 1446 | static int rate_get(void *data, u64 *val) |
1452 | { | 1447 | { |
1453 | struct gk20a *g = (struct gk20a *)data; | 1448 | struct gk20a *g = (struct gk20a *)data; |
1454 | *val = (u64)gk20a_clk_get_rate(g); | 1449 | struct clk_gk20a *clk = &g->clk; |
1450 | |||
1451 | *val = (u64)rate_gpc2clk_to_gpu(clk->gpc_pll.freq); | ||
1455 | return 0; | 1452 | return 0; |
1456 | } | 1453 | } |
1457 | static int rate_set(void *data, u64 val) | 1454 | static int rate_set(void *data, u64 val) |
1458 | { | 1455 | { |
1459 | struct gk20a *g = (struct gk20a *)data; | 1456 | struct gk20a *g = (struct gk20a *)data; |
1460 | return gk20a_clk_set_rate(g, (u32)val); | 1457 | return g->ops.clk.set_rate(g, CTRL_CLK_DOMAIN_GPCCLK, (u32)val); |
1461 | } | 1458 | } |
1462 | DEFINE_SIMPLE_ATTRIBUTE(rate_fops, rate_get, rate_set, "%llu\n"); | 1459 | DEFINE_SIMPLE_ATTRIBUTE(rate_fops, rate_get, rate_set, "%llu\n"); |
1463 | 1460 | ||