diff options
author | Alex Frid <afrid@nvidia.com> | 2018-08-28 21:13:28 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-08-30 23:17:10 -0400 |
commit | a6108a4b0ed52c7a8fa58d9815d0b373be8305bf (patch) | |
tree | b30a7635132b8d48fa8b1b7e31844a9ce5cfd778 /drivers/gpu/nvgpu/gm20b/clk_gm20b.c | |
parent | 9c60230b5723d6a0dbb83bf85d499a671491245f (diff) |
gpu: nvgpu: Fix GM20b GPCPLL debugfs node
GM20B GPCPLL registers are accessed via sys address space with the
exception of the last dvfs2 register that can be accessed only through
bcast address. However, in debugfs loop dvfs2 sys address should be
used as loop terminator; otherwise, loop body is never executed, and
GPCPLL registers debugfs node is broken. Fixed it in this commit.
Change-Id: Ifea839757fda7d97b2c9238178227ab198526ab0
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1808784
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/clk_gm20b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/clk_gm20b.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c index 93bae921..2ba677b0 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c | |||
@@ -1655,7 +1655,8 @@ int gm20b_clk_get_pll_debug_data(struct gk20a *g, | |||
1655 | d->trim_sys_gpc2clk_out_reg = trim_sys_gpc2clk_out_r(); | 1655 | d->trim_sys_gpc2clk_out_reg = trim_sys_gpc2clk_out_r(); |
1656 | d->trim_sys_gpc2clk_out_val = gk20a_readl(g, trim_sys_gpc2clk_out_r()); | 1656 | d->trim_sys_gpc2clk_out_val = gk20a_readl(g, trim_sys_gpc2clk_out_r()); |
1657 | d->trim_sys_gpcpll_cfg_reg = trim_sys_gpcpll_cfg_r(); | 1657 | d->trim_sys_gpcpll_cfg_reg = trim_sys_gpcpll_cfg_r(); |
1658 | d->trim_sys_gpcpll_dvfs2_reg = trim_gpc_bcast_gpcpll_dvfs2_r(); | 1658 | d->trim_sys_gpcpll_dvfs2_reg = trim_sys_gpcpll_dvfs2_r(); |
1659 | d->trim_bcast_gpcpll_dvfs2_reg = trim_gpc_bcast_gpcpll_dvfs2_r(); | ||
1659 | 1660 | ||
1660 | reg = gk20a_readl(g, trim_sys_gpcpll_cfg_r()); | 1661 | reg = gk20a_readl(g, trim_sys_gpcpll_cfg_r()); |
1661 | d->trim_sys_gpcpll_cfg_val = reg; | 1662 | d->trim_sys_gpcpll_cfg_val = reg; |