gpu: nvgpu: use fuse APIs from <nvgpu/fuse.h>

Remove <soc/tegra/fuse.h> includes and include
<nvgpu/fuse.h> header to remove direct dependency
on platform specific header

Use specific APIs like below to read/write fuses
nvgpu_tegra_fuse_write_bypass()
nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable()

Remove old code which was compiled for kernel versions
less than 4.4 since we support only k4.4 and greater
versions now

Jira NVGPU-75

Change-Id: Iddd8e1a8da7effbce2aff217e8e25f7de04962d6
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1497518
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

1 files changed, 1 insertions, 3 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c
index ceeb457a..8dfc5636 100644
--- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c
@@ -240,8 +240,6 @@ found_match:
 
 /* GPCPLL NA/DVFS mode methods */
 
-#define FUSE_RESERVED_CALIB 0x204
-
 static inline int fuse_get_gpcpll_adc_rev(u32 val)
 {
         return (val >> 30) & 0x3;
@@ -264,7 +262,7 @@ static int nvgpu_fuse_calib_gpcpll_get_adc(int *slope_uv, int *intercept_uv)
         u32 val;
         int ret;
 
-        ret = nvgpu_tegra_fuse_read(FUSE_RESERVED_CALIB, &val);
+        ret = nvgpu_tegra_fuse_read_reserved_calib(&val);
         if (ret)
                 return ret;