diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2017-03-17 14:09:44 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-03-23 11:44:07 -0400 |
commit | 4492c62ffe9398bd4457f6f1c2773e40afe909fb (patch) | |
tree | 5d792f81d97844278f4eca665a8b4778fa93dc35 /drivers/gpu/nvgpu/gm20b/bus_gm20b.c | |
parent | 33f637585ecd617a9f4423f56e2aa6df0691ac64 (diff) |
gpu: nvgpu: Add bus HAL
Add bus HAL and move all bus related hardware sequencing to that file:
BAR1 binding, timer access, and interrupt handling.
Change-Id: Ibc5f5797dc338de10749b446a7bdbcae600fecb4
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1323353
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/bus_gm20b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/bus_gm20b.c | 64 |
1 files changed, 64 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/bus_gm20b.c b/drivers/gpu/nvgpu/gm20b/bus_gm20b.c new file mode 100644 index 00000000..68a4b15f --- /dev/null +++ b/drivers/gpu/nvgpu/gm20b/bus_gm20b.c | |||
@@ -0,0 +1,64 @@ | |||
1 | /* | ||
2 | * GM20B MMU | ||
3 | * | ||
4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | */ | ||
15 | |||
16 | #include <linux/delay.h> | ||
17 | |||
18 | #include <nvgpu/timers.h> | ||
19 | |||
20 | #include "bus_gm20b.h" | ||
21 | #include "gk20a/gk20a.h" | ||
22 | #include "gk20a/bus_gk20a.h" | ||
23 | |||
24 | #include <nvgpu/hw/gm20b/hw_bus_gm20b.h> | ||
25 | |||
26 | static int gm20b_bus_bar1_bind(struct gk20a *g, struct mem_desc *bar1_inst) | ||
27 | { | ||
28 | struct nvgpu_timeout timeout; | ||
29 | int err = 0; | ||
30 | u64 iova = gk20a_mm_inst_block_addr(g, bar1_inst); | ||
31 | u32 ptr_v = (u32)(iova >> bar1_instance_block_shift_gk20a()); | ||
32 | |||
33 | gk20a_dbg_info("bar1 inst block ptr: 0x%08x", ptr_v); | ||
34 | |||
35 | gk20a_writel(g, bus_bar1_block_r(), | ||
36 | gk20a_aperture_mask(g, bar1_inst, | ||
37 | bus_bar1_block_target_sys_mem_ncoh_f(), | ||
38 | bus_bar1_block_target_vid_mem_f()) | | ||
39 | bus_bar1_block_mode_virtual_f() | | ||
40 | bus_bar1_block_ptr_f(ptr_v)); | ||
41 | nvgpu_timeout_init(g, &timeout, 1000, NVGPU_TIMER_RETRY_TIMER); | ||
42 | do { | ||
43 | u32 val = gk20a_readl(g, bus_bind_status_r()); | ||
44 | u32 pending = bus_bind_status_bar1_pending_v(val); | ||
45 | u32 outstanding = bus_bind_status_bar1_outstanding_v(val); | ||
46 | if (!pending && !outstanding) | ||
47 | break; | ||
48 | |||
49 | udelay(5); | ||
50 | } while (!nvgpu_timeout_expired(&timeout)); | ||
51 | |||
52 | if (nvgpu_timeout_peek_expired(&timeout)) | ||
53 | err = -EINVAL; | ||
54 | |||
55 | return err; | ||
56 | } | ||
57 | |||
58 | void gm20b_init_bus(struct gpu_ops *gops) | ||
59 | { | ||
60 | gops->bus.init_hw = gk20a_bus_init_hw; | ||
61 | gops->bus.isr = gk20a_bus_isr; | ||
62 | gops->bus.read_ptimer = gk20a_read_ptimer; | ||
63 | gops->bus.bar1_bind = gm20b_bus_bar1_bind; | ||
64 | } | ||