nvgpu: Modify ACR host to use physical trancfg

PMU ucode and ACR ucode need 0th ctx dma to be programmed
for Physical access. To stay in sync with ucodes,
modified 0th transcfg to be physical access, and suitably
modified all other ctx dma's sent.

Bug 1509680
Change-Id: Ib3a24ebb8478488af57bb465d782e4045ca7d0d0
Signed-off-by: Supriya <ssharatkumar@nvidia.com>
Reviewed-on: http://git-master/r/432084
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

1 files changed, 1 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h
index 84473c30..073dc135 100644
--- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h
@@ -301,8 +301,8 @@ struct flcn_acr_desc {
         u32 wpr_region_id;
         u32 wpr_offset;
         struct flcn_acr_regions regions;
-        u32 nonwpr_ucode_blob_start;
         u32 nonwpr_ucode_blob_size;
+        u64 nonwpr_ucode_blob_start;
 };
 
 /*!