diff options
author | Sunny He <suhe@nvidia.com> | 2017-08-01 20:10:42 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-08-21 16:06:07 -0400 |
commit | 5f010177de985c901c33c914efe70a8498a5974f (patch) | |
tree | 1b1a2ac1ab71608a0754a7eb64222f5d198e793c /drivers/gpu/nvgpu/gm20b/acr_gm20b.h | |
parent | b50b379c192714d0d08c3f2d33e90c95cf795253 (diff) |
gpu: nvgpu: Reorg pmu HAL initialization
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the
pmu sub-module of the gpu_ops struct.
Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.
Jira NVGPU-74
Change-Id: I8839ac99e87153637005e23b3013237f57275c54
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1530982
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/acr_gm20b.h')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/acr_gm20b.h | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h index 84478611..6568d62f 100644 --- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h | |||
@@ -24,8 +24,21 @@ | |||
24 | #define GM20B_FECS_UCODE_SIG "fecs_sig.bin" | 24 | #define GM20B_FECS_UCODE_SIG "fecs_sig.bin" |
25 | #define T18x_GPCCS_UCODE_SIG "gpccs_sig.bin" | 25 | #define T18x_GPCCS_UCODE_SIG "gpccs_sig.bin" |
26 | 26 | ||
27 | void gm20b_init_secure_pmu(struct gpu_ops *gops); | 27 | bool gm20b_is_pmu_supported(struct gk20a *g); |
28 | int prepare_ucode_blob(struct gk20a *g); | 28 | int prepare_ucode_blob(struct gk20a *g); |
29 | int gm20b_bootstrap_hs_flcn(struct gk20a *g); | ||
30 | bool gm20b_is_lazy_bootstrap(u32 falcon_id); | ||
31 | bool gm20b_is_priv_load(u32 falcon_id); | ||
32 | void gm20b_wpr_info(struct gk20a *g, struct wpr_carveout_info *inf); | ||
33 | int gm20b_alloc_blob_space(struct gk20a *g, size_t size, struct nvgpu_mem *mem); | ||
34 | int gm20b_pmu_populate_loader_cfg(struct gk20a *g, | ||
35 | void *lsfm, u32 *p_bl_gen_desc_size); | ||
36 | int gm20b_flcn_populate_bl_dmem_desc(struct gk20a *g, | ||
37 | void *lsfm, u32 *p_bl_gen_desc_size, u32 falconid); | ||
38 | int pmu_wait_for_halt(struct gk20a *g, unsigned int timeout_ms); | ||
39 | int clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout); | ||
40 | int gm20b_init_pmu_setup_hw1(struct gk20a *g, void *desc, u32 bl_sz); | ||
41 | |||
29 | int gm20b_pmu_setup_sw(struct gk20a *g); | 42 | int gm20b_pmu_setup_sw(struct gk20a *g); |
30 | int pmu_exec_gen_bl(struct gk20a *g, void *desc, u8 b_wait_for_halt); | 43 | int pmu_exec_gen_bl(struct gk20a *g, void *desc, u8 b_wait_for_halt); |
31 | int gm20b_init_nspmu_setup_hw1(struct gk20a *g); | 44 | int gm20b_init_nspmu_setup_hw1(struct gk20a *g); |