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authorsmadhavan <smadhavan@nvidia.com>2018-09-05 03:18:10 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-09-06 19:13:08 -0400
commit5cfd481cf5319d52f613cb5c5f66a1f643af5bed (patch)
tree7cb3ba23eb7c9e652b027898b76d8e90570d00bd /drivers/gpu/nvgpu/gm20b/acr_gm20b.h
parent935f05b741b1b8470862f5326affa0bea60263cb (diff)
nvgpu: gm20b: MISRA Rule 21.2 header gurad fixes
MISRA rule 21.2 doesn't allow the use of macro names which start with an underscore. These leading underscores are to be removed from the macro names. This patch will fix such violations caused by include guards by renaming them to follow the convention, 'NVGPU_PARENT-DIR_HEADER_H' JIRA NVGPU-1028 Change-Id: Ic60b2de8bb705f189134483fff1e2dff8ea96a12 Signed-off-by: smadhavan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1808186 GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/acr_gm20b.h')
-rw-r--r--drivers/gpu/nvgpu/gm20b/acr_gm20b.h8
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h
index e22da730..7c9743ab 100644
--- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * GM20B ACR 2 * GM20B ACR
3 * 3 *
4 * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a 6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"), 7 * copy of this software and associated documentation files (the "Software"),
@@ -22,8 +22,8 @@
22 * DEALINGS IN THE SOFTWARE. 22 * DEALINGS IN THE SOFTWARE.
23 */ 23 */
24 24
25#ifndef __ACR_GM20B_H_ 25#ifndef NVGPU_GM20B_ACR_GM20B_H
26#define __ACR_GM20B_H_ 26#define NVGPU_GM20B_ACR_GM20B_H
27 27
28#define GM20B_PMU_UCODE_IMAGE "gpmu_ucode_image.bin" 28#define GM20B_PMU_UCODE_IMAGE "gpmu_ucode_image.bin"
29#define GM20B_PMU_UCODE_DESC "gpmu_ucode_desc.bin" 29#define GM20B_PMU_UCODE_DESC "gpmu_ucode_desc.bin"
@@ -59,4 +59,4 @@ int acr_ucode_patch_sig(struct gk20a *g,
59 unsigned int *p_dbg_sig, 59 unsigned int *p_dbg_sig,
60 unsigned int *p_patch_loc, 60 unsigned int *p_patch_loc,
61 unsigned int *p_patch_ind); 61 unsigned int *p_patch_ind);
62#endif /*__ACR_GM20B_H_*/ 62#endif /*NVGPU_GM20B_ACR_GM20B_H*/