diff options
author | Mahantesh Kumbar <mkumbar@nvidia.com> | 2016-05-27 01:57:49 -0400 |
---|---|---|
committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-06-01 14:24:12 -0400 |
commit | 9d13ddc17d21e9d4d65530e713a8ca7daf1dd1e2 (patch) | |
tree | ab41276f98628e772567126867644c76e1986b86 /drivers/gpu/nvgpu/gm20b/acr_gm20b.c | |
parent | 772761e6f498cd4e9f869c7b57ec2ef70971d197 (diff) |
gpu: nvgpu: update HAL of ACR BL
-update HAL of ACR BL which can support
gm204/gm206 and DMATRFBASE method to global
JIRA DNVGPU-10
Change-Id: I56fc7ce040dadb6473f6f375ee6ce90783a046ad
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1154954
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/acr_gm20b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/acr_gm20b.c | 44 |
1 files changed, 20 insertions, 24 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c index 18ad818e..1b8e7b5f 100644 --- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c | |||
@@ -55,12 +55,9 @@ static void lsfm_init_wpr_contents(struct gk20a *g, struct ls_flcn_mgr *plsfm, | |||
55 | struct mem_desc *nonwpr); | 55 | struct mem_desc *nonwpr); |
56 | static void free_acr_resources(struct gk20a *g, struct ls_flcn_mgr *plsfm); | 56 | static void free_acr_resources(struct gk20a *g, struct ls_flcn_mgr *plsfm); |
57 | static int gm20b_pmu_populate_loader_cfg(struct gk20a *g, | 57 | static int gm20b_pmu_populate_loader_cfg(struct gk20a *g, |
58 | struct lsfm_managed_ucode_img *lsfm, | 58 | void *lsfm, u32 *p_bl_gen_desc_size); |
59 | union flcn_bl_generic_desc *p_bl_gen_desc, u32 *p_bl_gen_desc_size); | ||
60 | static int gm20b_flcn_populate_bl_dmem_desc(struct gk20a *g, | 59 | static int gm20b_flcn_populate_bl_dmem_desc(struct gk20a *g, |
61 | struct lsfm_managed_ucode_img *lsfm, | 60 | void *lsfm, u32 *p_bl_gen_desc_size, u32 falconid); |
62 | union flcn_bl_generic_desc *p_bl_gen_desc, u32 *p_bl_gen_desc_size, | ||
63 | u32 falconid); | ||
64 | static int gm20b_alloc_blob_space(struct gk20a *g, | 61 | static int gm20b_alloc_blob_space(struct gk20a *g, |
65 | size_t size, struct mem_desc *mem); | 62 | size_t size, struct mem_desc *mem); |
66 | static bool gm20b_is_priv_load(u32 falcon_id); | 63 | static bool gm20b_is_priv_load(u32 falcon_id); |
@@ -540,14 +537,14 @@ static int lsfm_discover_ucode_images(struct gk20a *g, | |||
540 | 537 | ||
541 | 538 | ||
542 | static int gm20b_pmu_populate_loader_cfg(struct gk20a *g, | 539 | static int gm20b_pmu_populate_loader_cfg(struct gk20a *g, |
543 | struct lsfm_managed_ucode_img *lsfm, | 540 | void *lsfm, u32 *p_bl_gen_desc_size) |
544 | union flcn_bl_generic_desc *p_bl_gen_desc, u32 *p_bl_gen_desc_size) | ||
545 | { | 541 | { |
546 | struct mc_carveout_info inf; | 542 | struct mc_carveout_info inf; |
547 | struct pmu_gk20a *pmu = &g->pmu; | 543 | struct pmu_gk20a *pmu = &g->pmu; |
548 | struct flcn_ucode_img *p_img = &(lsfm->ucode_img); | 544 | struct lsfm_managed_ucode_img *p_lsfm = |
549 | struct loader_config *ldr_cfg = | 545 | (struct lsfm_managed_ucode_img *)lsfm; |
550 | (struct loader_config *)(&p_bl_gen_desc->loader_cfg); | 546 | struct flcn_ucode_img *p_img = &(p_lsfm->ucode_img); |
547 | struct loader_config *ldr_cfg = &(p_lsfm->bl_gen_desc.loader_cfg); | ||
551 | u64 addr_base; | 548 | u64 addr_base; |
552 | struct pmu_ucode_desc *desc; | 549 | struct pmu_ucode_desc *desc; |
553 | u64 addr_code, addr_data; | 550 | u64 addr_code, addr_data; |
@@ -565,7 +562,7 @@ static int gm20b_pmu_populate_loader_cfg(struct gk20a *g, | |||
565 | The 32-bit addresses will be the upper 32-bits of the virtual or | 562 | The 32-bit addresses will be the upper 32-bits of the virtual or |
566 | physical addresses of each respective segment. | 563 | physical addresses of each respective segment. |
567 | */ | 564 | */ |
568 | addr_base = lsfm->lsb_header.ucode_off; | 565 | addr_base = p_lsfm->lsb_header.ucode_off; |
569 | g->ops.pmu.get_wpr(g, &inf.base, &inf.size); | 566 | g->ops.pmu.get_wpr(g, &inf.base, &inf.size); |
570 | addr_base += inf.base; | 567 | addr_base += inf.base; |
571 | gm20b_dbg_pmu("pmu loader cfg u32 addrbase %x\n", (u32)addr_base); | 568 | gm20b_dbg_pmu("pmu loader cfg u32 addrbase %x\n", (u32)addr_base); |
@@ -606,20 +603,20 @@ static int gm20b_pmu_populate_loader_cfg(struct gk20a *g, | |||
606 | ldr_cfg->argc = 1; | 603 | ldr_cfg->argc = 1; |
607 | ldr_cfg->argv = addr_args; | 604 | ldr_cfg->argv = addr_args; |
608 | 605 | ||
609 | *p_bl_gen_desc_size = sizeof(p_bl_gen_desc->loader_cfg); | 606 | *p_bl_gen_desc_size = sizeof(struct loader_config); |
610 | g->acr.pmu_args = addr_args; | 607 | g->acr.pmu_args = addr_args; |
611 | return 0; | 608 | return 0; |
612 | } | 609 | } |
613 | 610 | ||
614 | static int gm20b_flcn_populate_bl_dmem_desc(struct gk20a *g, | 611 | static int gm20b_flcn_populate_bl_dmem_desc(struct gk20a *g, |
615 | struct lsfm_managed_ucode_img *lsfm, | 612 | void *lsfm, u32 *p_bl_gen_desc_size, u32 falconid) |
616 | union flcn_bl_generic_desc *p_bl_gen_desc, u32 *p_bl_gen_desc_size, | ||
617 | u32 falconid) | ||
618 | { | 613 | { |
619 | struct mc_carveout_info inf; | 614 | struct mc_carveout_info inf; |
620 | struct flcn_ucode_img *p_img = &(lsfm->ucode_img); | 615 | struct lsfm_managed_ucode_img *p_lsfm = |
616 | (struct lsfm_managed_ucode_img *)lsfm; | ||
617 | struct flcn_ucode_img *p_img = &(p_lsfm->ucode_img); | ||
621 | struct flcn_bl_dmem_desc *ldr_cfg = | 618 | struct flcn_bl_dmem_desc *ldr_cfg = |
622 | (struct flcn_bl_dmem_desc *)(&p_bl_gen_desc->bl_dmem_desc); | 619 | &(p_lsfm->bl_gen_desc.bl_dmem_desc); |
623 | u64 addr_base; | 620 | u64 addr_base; |
624 | struct pmu_ucode_desc *desc; | 621 | struct pmu_ucode_desc *desc; |
625 | u64 addr_code, addr_data; | 622 | u64 addr_code, addr_data; |
@@ -637,14 +634,14 @@ static int gm20b_flcn_populate_bl_dmem_desc(struct gk20a *g, | |||
637 | The 32-bit addresses will be the upper 32-bits of the virtual or | 634 | The 32-bit addresses will be the upper 32-bits of the virtual or |
638 | physical addresses of each respective segment. | 635 | physical addresses of each respective segment. |
639 | */ | 636 | */ |
640 | addr_base = lsfm->lsb_header.ucode_off; | 637 | addr_base = p_lsfm->lsb_header.ucode_off; |
641 | g->ops.pmu.get_wpr(g, &inf.base, &inf.size); | 638 | g->ops.pmu.get_wpr(g, &inf.base, &inf.size); |
642 | if (falconid == LSF_FALCON_ID_GPCCS) | 639 | if (falconid == LSF_FALCON_ID_GPCCS) |
643 | addr_base += g->pmu.wpr_buf.gpu_va; | 640 | addr_base += g->pmu.wpr_buf.gpu_va; |
644 | else | 641 | else |
645 | addr_base += inf.base; | 642 | addr_base += inf.base; |
646 | gm20b_dbg_pmu("gen loader cfg %x u32 addrbase %x ID\n", (u32)addr_base, | 643 | gm20b_dbg_pmu("gen loader cfg %x u32 addrbase %x ID\n", (u32)addr_base, |
647 | lsfm->wpr_header.falcon_id); | 644 | p_lsfm->wpr_header.falcon_id); |
648 | addr_code = u64_lo32((addr_base + | 645 | addr_code = u64_lo32((addr_base + |
649 | desc->app_start_offset + | 646 | desc->app_start_offset + |
650 | desc->app_resident_code_offset) >> 8); | 647 | desc->app_resident_code_offset) >> 8); |
@@ -654,7 +651,7 @@ static int gm20b_flcn_populate_bl_dmem_desc(struct gk20a *g, | |||
654 | 651 | ||
655 | gm20b_dbg_pmu("gen cfg %x u32 addrcode %x & data %x load offset %xID\n", | 652 | gm20b_dbg_pmu("gen cfg %x u32 addrcode %x & data %x load offset %xID\n", |
656 | (u32)addr_code, (u32)addr_data, desc->bootloader_start_offset, | 653 | (u32)addr_code, (u32)addr_data, desc->bootloader_start_offset, |
657 | lsfm->wpr_header.falcon_id); | 654 | p_lsfm->wpr_header.falcon_id); |
658 | 655 | ||
659 | /* Populate the LOADER_CONFIG state */ | 656 | /* Populate the LOADER_CONFIG state */ |
660 | memset((void *) ldr_cfg, 0, sizeof(struct flcn_bl_dmem_desc)); | 657 | memset((void *) ldr_cfg, 0, sizeof(struct flcn_bl_dmem_desc)); |
@@ -664,7 +661,7 @@ static int gm20b_flcn_populate_bl_dmem_desc(struct gk20a *g, | |||
664 | ldr_cfg->data_dma_base = addr_data; | 661 | ldr_cfg->data_dma_base = addr_data; |
665 | ldr_cfg->data_size = desc->app_resident_data_size; | 662 | ldr_cfg->data_size = desc->app_resident_data_size; |
666 | ldr_cfg->code_entry_point = desc->app_imem_entry; | 663 | ldr_cfg->code_entry_point = desc->app_imem_entry; |
667 | *p_bl_gen_desc_size = sizeof(p_bl_gen_desc->bl_dmem_desc); | 664 | *p_bl_gen_desc_size = sizeof(struct flcn_bl_dmem_desc); |
668 | return 0; | 665 | return 0; |
669 | } | 666 | } |
670 | 667 | ||
@@ -677,8 +674,7 @@ static int lsfm_fill_flcn_bl_gen_desc(struct gk20a *g, | |||
677 | if (pnode->wpr_header.falcon_id != pmu->falcon_id) { | 674 | if (pnode->wpr_header.falcon_id != pmu->falcon_id) { |
678 | gm20b_dbg_pmu("non pmu. write flcn bl gen desc\n"); | 675 | gm20b_dbg_pmu("non pmu. write flcn bl gen desc\n"); |
679 | g->ops.pmu.flcn_populate_bl_dmem_desc(g, | 676 | g->ops.pmu.flcn_populate_bl_dmem_desc(g, |
680 | pnode, &pnode->bl_gen_desc, | 677 | pnode, &pnode->bl_gen_desc_size, |
681 | &pnode->bl_gen_desc_size, | ||
682 | pnode->wpr_header.falcon_id); | 678 | pnode->wpr_header.falcon_id); |
683 | return 0; | 679 | return 0; |
684 | } | 680 | } |
@@ -687,7 +683,7 @@ static int lsfm_fill_flcn_bl_gen_desc(struct gk20a *g, | |||
687 | gm20b_dbg_pmu("pmu write flcn bl gen desc\n"); | 683 | gm20b_dbg_pmu("pmu write flcn bl gen desc\n"); |
688 | if (pnode->wpr_header.falcon_id == pmu->falcon_id) | 684 | if (pnode->wpr_header.falcon_id == pmu->falcon_id) |
689 | return g->ops.pmu.pmu_populate_loader_cfg(g, pnode, | 685 | return g->ops.pmu.pmu_populate_loader_cfg(g, pnode, |
690 | &pnode->bl_gen_desc, &pnode->bl_gen_desc_size); | 686 | &pnode->bl_gen_desc_size); |
691 | } | 687 | } |
692 | 688 | ||
693 | /* Failed to find the falcon requested. */ | 689 | /* Failed to find the falcon requested. */ |