gpu: nvgpu: Falcon controller halt interrupt status clear

- Added nvgpu_flcn_clear_halt_intr_status() to
Wait for halt interrupt status clear by
clear_halt_interrupt_status() HAL within timeout

- Added gk20a_flcn_clear_halt_interrupt_status()
to clear falcon controller halt interrupt status

- Replaced flacon halt interrupt clear with
nvgpu_flcn_clear_halt_intr_status() method

NVGPU JIRA-99

Change-Id: I762a3c01cd1d02028eb6aaa9898a50be94376619
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master/r/1511333
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>

1 files changed, 5 insertions, 17 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
index e440e179..ee861933 100644
--- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
@@ -1517,23 +1517,11 @@ static int pmu_wait_for_halt(struct gk20a *g, unsigned int timeout_ms)
 */
 static int clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout_ms)
 {
-        u32 data = 0;
-        struct nvgpu_timeout timeout;
-
-        nvgpu_timeout_init(g, &timeout, timeout_ms, NVGPU_TIMER_CPU_TIMER);
-
-        do {
-                gk20a_writel(g, pwr_falcon_irqsclr_r(),
-                             gk20a_readl(g, pwr_falcon_irqsclr_r()) | (0x10));
-                data = gk20a_readl(g, (pwr_falcon_irqstat_r()));
-
-                if ((data & pwr_falcon_irqstat_halt_true_f()) !=
-                        pwr_falcon_irqstat_halt_true_f())
-                        /*halt irq is clear*/
-                        return 0;
+        struct nvgpu_pmu *pmu = &g->pmu;
+        int status = 0;
 
-                nvgpu_udelay(1);
-        } while (!nvgpu_timeout_expired(&timeout));
+        if (nvgpu_flcn_clear_halt_intr_status(pmu->flcn, timeout_ms))
+                status = -EBUSY;
 
-        return -ETIMEDOUT;
+        return status;
 }