diff options
author | Mahantesh Kumbar <mkumbar@nvidia.com> | 2017-02-14 02:22:20 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-02-15 22:33:28 -0500 |
commit | d465504534b2ec7ab0be190fc98b24e1b77634e2 (patch) | |
tree | 3ee1a90cb49cb2a3df3b39c79b37bdbcddeffe97 /drivers/gpu/nvgpu/gm206/pmu_gm206.c | |
parent | 907adfd785e3a3582b2649c48bf4c32f41745e3f (diff) |
gpu: nvgpu: Remove PMU gm204/gm206 support
-Created new methods for PMU gp106 whichever dependent
on gm206.
-Deleted pmu_gm206.c/h files & removed its involvement
from dependent files.
Change-Id: Ic578da53bff362efb3e142962275227787206233
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1304492
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm206/pmu_gm206.c')
-rw-r--r-- | drivers/gpu/nvgpu/gm206/pmu_gm206.c | 174 |
1 files changed, 0 insertions, 174 deletions
diff --git a/drivers/gpu/nvgpu/gm206/pmu_gm206.c b/drivers/gpu/nvgpu/gm206/pmu_gm206.c deleted file mode 100644 index ffcf0bf1..00000000 --- a/drivers/gpu/nvgpu/gm206/pmu_gm206.c +++ /dev/null | |||
@@ -1,174 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | |||
14 | #include <linux/delay.h> | ||
15 | |||
16 | #include "gk20a/gk20a.h" | ||
17 | #include "gk20a/pmu_gk20a.h" | ||
18 | #include "gk20a/pmu_gk20a.h" | ||
19 | #include "gm20b/acr_gm20b.h" | ||
20 | #include "gm206/acr_gm206.h" | ||
21 | #include "gm20b/pmu_gm20b.h" | ||
22 | #include "gm206/pmu_gm206.h" | ||
23 | |||
24 | #include <nvgpu/hw/gm206/hw_gr_gm206.h> | ||
25 | #include <nvgpu/hw/gm206/hw_pwr_gm206.h> | ||
26 | |||
27 | #define gm206_dbg_pmu(fmt, arg...) \ | ||
28 | gk20a_dbg(gpu_dbg_pmu, fmt, ##arg) | ||
29 | |||
30 | bool gm206_is_lazy_bootstrap(u32 falcon_id) | ||
31 | { | ||
32 | bool enable_status = false; | ||
33 | |||
34 | switch (falcon_id) { | ||
35 | case LSF_FALCON_ID_FECS: | ||
36 | enable_status = true; | ||
37 | break; | ||
38 | case LSF_FALCON_ID_GPCCS: | ||
39 | enable_status = true; | ||
40 | break; | ||
41 | default: | ||
42 | break; | ||
43 | } | ||
44 | |||
45 | return enable_status; | ||
46 | } | ||
47 | |||
48 | bool gm206_is_priv_load(u32 falcon_id) | ||
49 | { | ||
50 | bool enable_status = false; | ||
51 | |||
52 | switch (falcon_id) { | ||
53 | case LSF_FALCON_ID_FECS: | ||
54 | enable_status = true; | ||
55 | break; | ||
56 | case LSF_FALCON_ID_GPCCS: | ||
57 | enable_status = true; | ||
58 | break; | ||
59 | default: | ||
60 | break; | ||
61 | } | ||
62 | |||
63 | return enable_status; | ||
64 | } | ||
65 | |||
66 | static void gm206_pmu_load_multiple_falcons(struct gk20a *g, u32 falconidmask, | ||
67 | u32 flags) | ||
68 | { | ||
69 | struct pmu_gk20a *pmu = &g->pmu; | ||
70 | struct pmu_cmd cmd; | ||
71 | u32 seq; | ||
72 | |||
73 | gk20a_dbg_fn(""); | ||
74 | |||
75 | gm206_dbg_pmu("wprinit status = %x\n", g->ops.pmu.lspmuwprinitdone); | ||
76 | if (g->ops.pmu.lspmuwprinitdone) { | ||
77 | /* send message to load FECS falcon */ | ||
78 | memset(&cmd, 0, sizeof(struct pmu_cmd)); | ||
79 | cmd.hdr.unit_id = PMU_UNIT_ACR; | ||
80 | cmd.hdr.size = PMU_CMD_HDR_SIZE + | ||
81 | sizeof(struct pmu_acr_cmd_bootstrap_multiple_falcons); | ||
82 | cmd.cmd.acr.boot_falcons.cmd_type = | ||
83 | PMU_ACR_CMD_ID_BOOTSTRAP_MULTIPLE_FALCONS; | ||
84 | cmd.cmd.acr.boot_falcons.flags = flags; | ||
85 | cmd.cmd.acr.boot_falcons.falconidmask = | ||
86 | falconidmask; | ||
87 | cmd.cmd.acr.boot_falcons.usevamask = 0; | ||
88 | cmd.cmd.acr.boot_falcons.wprvirtualbase.lo = 0; | ||
89 | cmd.cmd.acr.boot_falcons.wprvirtualbase.hi = 0; | ||
90 | |||
91 | gm206_dbg_pmu("PMU_ACR_CMD_ID_BOOTSTRAP_MULTIPLE_FALCONS:%x\n", | ||
92 | falconidmask); | ||
93 | gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, | ||
94 | pmu_handle_fecs_boot_acr_msg, pmu, &seq, ~0); | ||
95 | } | ||
96 | |||
97 | gk20a_dbg_fn("done"); | ||
98 | } | ||
99 | |||
100 | int gm206_load_falcon_ucode(struct gk20a *g, u32 falconidmask) | ||
101 | { | ||
102 | u32 flags = PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES; | ||
103 | |||
104 | /* GM20B PMU supports loading FECS and GPCCS only */ | ||
105 | if (falconidmask == 0) | ||
106 | return -EINVAL; | ||
107 | if (falconidmask & ~((1 << LSF_FALCON_ID_FECS) | | ||
108 | (1 << LSF_FALCON_ID_GPCCS))) | ||
109 | return -EINVAL; | ||
110 | g->ops.pmu.lsfloadedfalconid = 0; | ||
111 | /* check whether pmu is ready to bootstrap lsf if not wait for it */ | ||
112 | if (!g->ops.pmu.lspmuwprinitdone) { | ||
113 | pmu_wait_message_cond(&g->pmu, | ||
114 | gk20a_get_gr_idle_timeout(g), | ||
115 | &g->ops.pmu.lspmuwprinitdone, 1); | ||
116 | /* check again if it still not ready indicate an error */ | ||
117 | if (!g->ops.pmu.lspmuwprinitdone) { | ||
118 | gk20a_err(dev_from_gk20a(g), | ||
119 | "PMU not ready to load LSF"); | ||
120 | return -ETIMEDOUT; | ||
121 | } | ||
122 | } | ||
123 | /* load falcon(s) */ | ||
124 | gm206_pmu_load_multiple_falcons(g, falconidmask, flags); | ||
125 | pmu_wait_message_cond(&g->pmu, | ||
126 | gk20a_get_gr_idle_timeout(g), | ||
127 | &g->ops.pmu.lsfloadedfalconid, falconidmask); | ||
128 | if (g->ops.pmu.lsfloadedfalconid != falconidmask) | ||
129 | return -ETIMEDOUT; | ||
130 | return 0; | ||
131 | } | ||
132 | |||
133 | static bool gm206_is_pmu_supported(struct gk20a *g) | ||
134 | { | ||
135 | return true; | ||
136 | } | ||
137 | |||
138 | |||
139 | void gm206_init_pmu_ops(struct gpu_ops *gops) | ||
140 | { | ||
141 | gops->pmu.is_pmu_supported = gm206_is_pmu_supported; | ||
142 | if (gops->privsecurity) { | ||
143 | gm206_init_secure_pmu(gops); | ||
144 | gops->pmu.init_wpr_region = gm20b_pmu_init_acr; | ||
145 | gops->pmu.load_lsfalcon_ucode = gm206_load_falcon_ucode; | ||
146 | gops->pmu.is_lazy_bootstrap = gm206_is_lazy_bootstrap; | ||
147 | gops->pmu.is_priv_load = gm206_is_priv_load; | ||
148 | } else { | ||
149 | gk20a_init_pmu_ops(gops); | ||
150 | gops->pmu.pmu_setup_hw_and_bootstrap = | ||
151 | gm20b_init_nspmu_setup_hw1; | ||
152 | gops->pmu.load_lsfalcon_ucode = NULL; | ||
153 | gops->pmu.init_wpr_region = NULL; | ||
154 | } | ||
155 | gops->pmu.pmu_setup_elpg = NULL; | ||
156 | gops->pmu.pmu_get_queue_head = pwr_pmu_queue_head_r; | ||
157 | gops->pmu.pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v; | ||
158 | gops->pmu.pmu_get_queue_tail = pwr_pmu_queue_tail_r; | ||
159 | gops->pmu.pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v; | ||
160 | gops->pmu.lspmuwprinitdone = 0; | ||
161 | gops->pmu.fecsbootstrapdone = false; | ||
162 | gops->pmu.write_dmatrfbase = gm20b_write_dmatrfbase; | ||
163 | gops->pmu.pmu_elpg_statistics = NULL; | ||
164 | gops->pmu.pmu_pg_init_param = NULL; | ||
165 | gops->pmu.pmu_pg_supported_engines_list = NULL; | ||
166 | gops->pmu.pmu_pg_engines_feature_list = NULL; | ||
167 | gops->pmu.pmu_lpwr_enable_pg = NULL; | ||
168 | gops->pmu.pmu_is_lpwr_feature_supported = NULL; | ||
169 | gops->pmu.pmu_lpwr_disable_pg = NULL; | ||
170 | gops->pmu.pmu_pg_param_post_init = NULL; | ||
171 | gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = NULL; | ||
172 | gops->pmu.dump_secure_fuses = NULL; | ||
173 | gops->pmu.reset = gk20a_pmu_reset; | ||
174 | } | ||