gpu: nvgpu: Add multiple engine and runlist support

This CL covers the following modification,
1) Added multiple engine_info support
2) Added multiple runlist_info support
3) Initial changes for ASYNC CE support
4) Added ASYNC CE interrupt handling support
   for gm206 GPU family
5) Added generic mechanism to identify the
   CE engine pri_base address for gm206
   (CE0, CE1 and CE2)
6) Removed hard coded engine_id logic and
   made generic way
7) Code cleanup for readability

JIRA DNVGPU-26

Change-Id: I2c3846c40bcc8d10c2dfb225caa4105fc9123b65
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1155963
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 2 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gm206/fifo_gm206.c b/drivers/gpu/nvgpu/gm206/fifo_gm206.c
index c78f256c..6caf30f4 100644
--- a/drivers/gpu/nvgpu/gm206/fifo_gm206.c
+++ b/drivers/gpu/nvgpu/gm206/fifo_gm206.c
@@ -18,6 +18,7 @@
 #include "gm20b/fifo_gm20b.h"
 #include "fifo_gm206.h"
 #include "hw_ccsr_gm206.h"
+#include "hw_fifo_gm206.h"
 
 static u32 gm206_fifo_get_num_fifos(struct gk20a *g)
 {
@@ -28,4 +29,5 @@ void gm206_init_fifo(struct gpu_ops *gops)
 {
         gm20b_init_fifo(gops);
         gops->fifo.get_num_fifos = gm206_fifo_get_num_fifos;
+        gops->fifo.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v;
 }