diff options
| author | Terje Bergstrom <tbergstrom@nvidia.com> | 2017-04-20 17:08:26 -0400 |
|---|---|---|
| committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-04-21 02:11:31 -0400 |
| commit | 13bebeced17c206995bd17c573d094968cc0fbca (patch) | |
| tree | 3892a00b5d083ad96dbe2ddbf7a9386c14afe660 /drivers/gpu/nvgpu/gm206/bios_gm206.c | |
| parent | e32f62fadfcde413bcd9b5af61ad884e27ba2bf1 (diff) | |
gpu: nvgpu: Use retry timer for short delays
CPU timer is inaccurate for short delays, and can produce false
timeouts.
Bug 1903521
Change-Id: I688b5a59489b62cbd59e418d641fd188ecd3b7e0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1467002
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm206/bios_gm206.c')
| -rw-r--r-- | drivers/gpu/nvgpu/gm206/bios_gm206.c | 22 |
1 files changed, 15 insertions, 7 deletions
diff --git a/drivers/gpu/nvgpu/gm206/bios_gm206.c b/drivers/gpu/nvgpu/gm206/bios_gm206.c index f460a053..6db37d72 100644 --- a/drivers/gpu/nvgpu/gm206/bios_gm206.c +++ b/drivers/gpu/nvgpu/gm206/bios_gm206.c | |||
| @@ -105,8 +105,10 @@ static int gm206_bios_devinit(struct gk20a *g) | |||
| 105 | gk20a_dbg_fn(""); | 105 | gk20a_dbg_fn(""); |
| 106 | g->ops.pmu.reset(g); | 106 | g->ops.pmu.reset(g); |
| 107 | 107 | ||
| 108 | nvgpu_timeout_init(g, &timeout, PMU_BOOT_TIMEOUT_MAX / 1000, | 108 | nvgpu_timeout_init(g, &timeout, |
| 109 | NVGPU_TIMER_CPU_TIMER); | 109 | PMU_BOOT_TIMEOUT_MAX / |
| 110 | PMU_BOOT_TIMEOUT_DEFAULT, | ||
| 111 | NVGPU_TIMER_RETRY_TIMER); | ||
| 110 | do { | 112 | do { |
| 111 | u32 w = gk20a_readl(g, pwr_falcon_dmactl_r()) & | 113 | u32 w = gk20a_readl(g, pwr_falcon_dmactl_r()) & |
| 112 | (pwr_falcon_dmactl_dmem_scrubbing_m() | | 114 | (pwr_falcon_dmactl_dmem_scrubbing_m() | |
| @@ -152,8 +154,10 @@ static int gm206_bios_devinit(struct gk20a *g) | |||
| 152 | gk20a_writel(g, pwr_falcon_cpuctl_r(), | 154 | gk20a_writel(g, pwr_falcon_cpuctl_r(), |
| 153 | pwr_falcon_cpuctl_startcpu_f(1)); | 155 | pwr_falcon_cpuctl_startcpu_f(1)); |
| 154 | 156 | ||
| 155 | nvgpu_timeout_init(g, &timeout, PMU_BOOT_TIMEOUT_MAX / 1000, | 157 | nvgpu_timeout_init(g, &timeout, |
| 156 | NVGPU_TIMER_CPU_TIMER); | 158 | PMU_BOOT_TIMEOUT_MAX / |
| 159 | PMU_BOOT_TIMEOUT_DEFAULT, | ||
| 160 | NVGPU_TIMER_RETRY_TIMER); | ||
| 157 | do { | 161 | do { |
| 158 | devinit_completed = pwr_falcon_cpuctl_halt_intr_v( | 162 | devinit_completed = pwr_falcon_cpuctl_halt_intr_v( |
| 159 | gk20a_readl(g, pwr_falcon_cpuctl_r())) && | 163 | gk20a_readl(g, pwr_falcon_cpuctl_r())) && |
| @@ -183,8 +187,10 @@ static int gm206_bios_preos(struct gk20a *g) | |||
| 183 | gk20a_dbg_fn(""); | 187 | gk20a_dbg_fn(""); |
| 184 | g->ops.pmu.reset(g); | 188 | g->ops.pmu.reset(g); |
| 185 | 189 | ||
| 186 | nvgpu_timeout_init(g, &timeout, PMU_BOOT_TIMEOUT_MAX / 1000, | 190 | nvgpu_timeout_init(g, &timeout, |
| 187 | NVGPU_TIMER_CPU_TIMER); | 191 | PMU_BOOT_TIMEOUT_MAX / |
| 192 | PMU_BOOT_TIMEOUT_DEFAULT, | ||
| 193 | NVGPU_TIMER_RETRY_TIMER); | ||
| 188 | do { | 194 | do { |
| 189 | u32 w = gk20a_readl(g, pwr_falcon_dmactl_r()) & | 195 | u32 w = gk20a_readl(g, pwr_falcon_dmactl_r()) & |
| 190 | (pwr_falcon_dmactl_dmem_scrubbing_m() | | 196 | (pwr_falcon_dmactl_dmem_scrubbing_m() | |
| @@ -222,7 +228,9 @@ static int gm206_bios_preos(struct gk20a *g) | |||
| 222 | gk20a_writel(g, pwr_falcon_cpuctl_r(), | 228 | gk20a_writel(g, pwr_falcon_cpuctl_r(), |
| 223 | pwr_falcon_cpuctl_startcpu_f(1)); | 229 | pwr_falcon_cpuctl_startcpu_f(1)); |
| 224 | 230 | ||
| 225 | nvgpu_timeout_init(g, &timeout, PMU_BOOT_TIMEOUT_MAX / 1000, | 231 | nvgpu_timeout_init(g, &timeout, |
| 232 | PMU_BOOT_TIMEOUT_MAX / | ||
| 233 | PMU_BOOT_TIMEOUT_DEFAULT, | ||
| 226 | NVGPU_TIMER_CPU_TIMER); | 234 | NVGPU_TIMER_CPU_TIMER); |
| 227 | do { | 235 | do { |
| 228 | val = pwr_falcon_cpuctl_halt_intr_v( | 236 | val = pwr_falcon_cpuctl_halt_intr_v( |