diff options
author | Deepak Nibade <dnibade@nvidia.com> | 2018-04-20 10:10:16 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-04-24 14:10:48 -0400 |
commit | fc1ebe57f506c658eb771c101f256b02e3f351ce (patch) | |
tree | 25de8cf88b99d3612d5008d6cd7d27c3349e8904 /drivers/gpu/nvgpu/gk20a | |
parent | 65a543f5cac32686b6b2a57b93e285de6aae4ece (diff) |
gpu: nvgpu: add HALs to submit and wait for runlist
Add below two new HALs
gops.fifo.runlist_hw_submit() to submit a new runlist to hardware
gops.fifo.runlist_wait_pending() to wait until runlist write is successful
Set existing API gk20a_fifo_runlist_wait_pending() to
gops.fifo.runlist_wait_pending HAL
Add new API gk20a_fifo_runlist_hw_submit() which submits the runlist to h/w
and set it to gops.fifo.runlist_hw_submit HAL
Jira NVGPUT-20
Change-Id: Ic23f7d947e30883aca0b536de818e79e14733195
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1700548
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 40 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 3 |
3 files changed, 31 insertions, 14 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index c446e3ea..709631d4 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -3217,6 +3217,29 @@ int gk20a_fifo_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice) | |||
3217 | return g->ops.fifo.update_runlist(g, tsg->runlist_id, ~0, true, true); | 3217 | return g->ops.fifo.update_runlist(g, tsg->runlist_id, ~0, true, true); |
3218 | } | 3218 | } |
3219 | 3219 | ||
3220 | void gk20a_fifo_runlist_hw_submit(struct gk20a *g, u32 runlist_id, | ||
3221 | u32 count, u32 buffer_index) | ||
3222 | { | ||
3223 | struct fifo_runlist_info_gk20a *runlist = NULL; | ||
3224 | u64 runlist_iova; | ||
3225 | |||
3226 | runlist = &g->fifo.runlist_info[runlist_id]; | ||
3227 | runlist_iova = nvgpu_mem_get_addr(g, &runlist->mem[buffer_index]); | ||
3228 | |||
3229 | if (count != 0) { | ||
3230 | gk20a_writel(g, fifo_runlist_base_r(), | ||
3231 | fifo_runlist_base_ptr_f(u64_lo32(runlist_iova >> 12)) | | ||
3232 | nvgpu_aperture_mask(g, &runlist->mem[buffer_index], | ||
3233 | fifo_runlist_base_target_sys_mem_ncoh_f(), | ||
3234 | fifo_runlist_base_target_sys_mem_coh_f(), | ||
3235 | fifo_runlist_base_target_vid_mem_f())); | ||
3236 | } | ||
3237 | |||
3238 | gk20a_writel(g, fifo_runlist_r(), | ||
3239 | fifo_runlist_engine_f(runlist_id) | | ||
3240 | fifo_eng_runlist_length_f(count)); | ||
3241 | } | ||
3242 | |||
3220 | static int gk20a_fifo_update_runlist_locked(struct gk20a *g, u32 runlist_id, | 3243 | static int gk20a_fifo_update_runlist_locked(struct gk20a *g, u32 runlist_id, |
3221 | u32 chid, bool add, | 3244 | u32 chid, bool add, |
3222 | bool wait_for_finish) | 3245 | bool wait_for_finish) |
@@ -3297,21 +3320,10 @@ static int gk20a_fifo_update_runlist_locked(struct gk20a *g, u32 runlist_id, | |||
3297 | } else /* suspend to remove all channels */ | 3320 | } else /* suspend to remove all channels */ |
3298 | count = 0; | 3321 | count = 0; |
3299 | 3322 | ||
3300 | if (count != 0) { | 3323 | g->ops.fifo.runlist_hw_submit(g, runlist_id, count, new_buf); |
3301 | gk20a_writel(g, fifo_runlist_base_r(), | ||
3302 | fifo_runlist_base_ptr_f(u64_lo32(runlist_iova >> 12)) | | ||
3303 | nvgpu_aperture_mask(g, &runlist->mem[new_buf], | ||
3304 | fifo_runlist_base_target_sys_mem_ncoh_f(), | ||
3305 | fifo_runlist_base_target_sys_mem_coh_f(), | ||
3306 | fifo_runlist_base_target_vid_mem_f())); | ||
3307 | } | ||
3308 | |||
3309 | gk20a_writel(g, fifo_runlist_r(), | ||
3310 | fifo_runlist_engine_f(runlist_id) | | ||
3311 | fifo_eng_runlist_length_f(count)); | ||
3312 | 3324 | ||
3313 | if (wait_for_finish) { | 3325 | if (wait_for_finish) { |
3314 | ret = gk20a_fifo_runlist_wait_pending(g, runlist_id); | 3326 | ret = g->ops.fifo.runlist_wait_pending(g, runlist_id); |
3315 | 3327 | ||
3316 | if (ret == -ETIMEDOUT) { | 3328 | if (ret == -ETIMEDOUT) { |
3317 | nvgpu_err(g, | 3329 | nvgpu_err(g, |
@@ -3321,7 +3333,7 @@ static int gk20a_fifo_update_runlist_locked(struct gk20a *g, u32 runlist_id, | |||
3321 | 3333 | ||
3322 | /* engine reset needs the lock. drop it */ | 3334 | /* engine reset needs the lock. drop it */ |
3323 | /* wait until the runlist is active again */ | 3335 | /* wait until the runlist is active again */ |
3324 | ret = gk20a_fifo_runlist_wait_pending(g, runlist_id); | 3336 | ret = g->ops.fifo.runlist_wait_pending(g, runlist_id); |
3325 | /* get the lock back. at this point everything should | 3337 | /* get the lock back. at this point everything should |
3326 | * should be fine */ | 3338 | * should be fine */ |
3327 | 3339 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h index 12ef5f69..ea9f4528 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | |||
@@ -385,6 +385,8 @@ u32 *gk20a_runlist_construct_locked(struct fifo_gk20a *f, | |||
385 | bool interleave_enabled, | 385 | bool interleave_enabled, |
386 | bool prev_empty, | 386 | bool prev_empty, |
387 | u32 *entries_left); | 387 | u32 *entries_left); |
388 | void gk20a_fifo_runlist_hw_submit(struct gk20a *g, u32 runlist_id, | ||
389 | u32 count, u32 buffer_index); | ||
388 | int gk20a_fifo_runlist_wait_pending(struct gk20a *g, u32 runlist_id); | 390 | int gk20a_fifo_runlist_wait_pending(struct gk20a *g, u32 runlist_id); |
389 | int gk20a_init_fifo_setup_sw_common(struct gk20a *g); | 391 | int gk20a_init_fifo_setup_sw_common(struct gk20a *g); |
390 | int gk20a_init_fifo_setup_sw(struct gk20a *g); | 392 | int gk20a_init_fifo_setup_sw(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 57854e11..ba27f5d9 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -669,6 +669,9 @@ struct gpu_ops { | |||
669 | u64 *base_gpuva, u32 *sync_size); | 669 | u64 *base_gpuva, u32 *sync_size); |
670 | u32 (*get_syncpt_incr_per_release)(void); | 670 | u32 (*get_syncpt_incr_per_release)(void); |
671 | #endif | 671 | #endif |
672 | void (*runlist_hw_submit)(struct gk20a *g, u32 runlist_id, | ||
673 | u32 count, u32 buffer_index); | ||
674 | int (*runlist_wait_pending)(struct gk20a *g, u32 runlist_id); | ||
672 | } fifo; | 675 | } fifo; |
673 | struct pmu_v { | 676 | struct pmu_v { |
674 | u32 (*get_pmu_cmdline_args_size)(struct nvgpu_pmu *pmu); | 677 | u32 (*get_pmu_cmdline_args_size)(struct nvgpu_pmu *pmu); |