gpu: nvgpu: Initial Nvlink driver skeleton

Adds the skeleton and integration of the GV100 endpoint driver to NVGPU

(1) Adds a OS abstraction layer for the internal nvlink structure.
(2) Adds linux specific integration with Nvlink core driver.
(3) Adds function pointers for nvlink api, initialization and isr process.
(4) Adds initial support for minion.
(5) Adds new GPU enable properties to handle NVLINK presence
(6) Adds new GPU enable properties for SG_PHY bypass (required for NVLINK over
PCI)
(7) Adds parsing of nvlink vbios structures.
(8) Adds logging defines for NVGPU

JIRA: EVLR-2328

Change-Id: I0720a165a15c7187892c8c1a0662ec598354ac06
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1644708
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2 files changed, 39 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c
index b4886e31..868792c0 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.c
@@ -186,6 +186,18 @@ int gk20a_finalize_poweron(struct gk20a *g)
                 }
         }
 
+        if (nvgpu_is_enabled(g, NVGPU_SUPPORT_NVLINK)) {
+                if (g->ops.nvlink.init) {
+                        err = g->ops.nvlink.init(g);
+                        if (err) {
+                                nvgpu_err(g, "failed to init nvlink");
+                                __nvgpu_set_enabled(g, NVGPU_SUPPORT_NVLINK,
+                                                                        false);
+                        }
+                } else
+                        __nvgpu_set_enabled(g, NVGPU_SUPPORT_NVLINK, false);
+        }
+
         if (g->ops.fb.mem_unlock) {
                 err = g->ops.fb.mem_unlock(g);
                 if (err) {
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index cc62865c..f187f730 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -62,6 +62,7 @@ struct nvgpu_ctxsw_trace_filter;
 #include <nvgpu/barrier.h>
 #include <nvgpu/rwsem.h>
 #include <nvgpu/clk_arb.h>
+#include <nvgpu/nvlink.h>
 
 #include "clk_gk20a.h"
 #include "ce2_gk20a.h"
@@ -961,6 +962,7 @@ struct gpu_ops {
                                 bool enable, bool is_stalling, u32 unit);
                 void (*isr_stall)(struct gk20a *g);
                 bool (*is_intr_hub_pending)(struct gk20a *g, u32 mc_intr);
+                bool (*is_intr_nvlink_pending)(struct gk20a *g, u32 mc_intr);
                 u32 (*intr_stall)(struct gk20a *g);
                 void (*intr_stall_pause)(struct gk20a *g);
                 void (*intr_stall_resume)(struct gk20a *g);
@@ -1057,7 +1059,27 @@ struct gpu_ops {
         struct {
                 int (*check_priv_security)(struct gk20a *g);
         } fuse;
-
+        struct {
+                u32 (*init)(struct gk20a *g);
+                u32 (*discover_ioctrl)(struct gk20a *g);
+                u32 (*discover_link)(struct gk20a *g);
+                u32 (*isr)(struct gk20a *g);
+                /* API */
+                int (*link_early_init)(struct gk20a *g, unsigned long mask);
+                u32 (*link_get_mode)(struct gk20a *g, u32 link_id);
+                u32 (*link_get_state)(struct gk20a *g, u32 link_id);
+                int (*link_set_mode)(struct gk20a *g, u32 link_id, u32 mode);
+                u32 (*get_sublink_mode)(struct gk20a *g, u32 link_id,
+                        bool is_rx_sublink);
+                u32 (*get_rx_sublink_state)(struct gk20a *g, u32 link_id);
+                u32 (*get_tx_sublink_state)(struct gk20a *g, u32 link_id);
+                int (*set_sublink_mode)(struct gk20a *g, u32 link_id,
+                        bool is_rx_sublink, u32 mode);
+                int (*interface_init)(struct gk20a *g);
+                int (*reg_init)(struct gk20a *g);
+                int (*shutdown)(struct gk20a *g);
+                int (*early_init)(struct gk20a *g);
+        } nvlink;
 };
 
 struct nvgpu_bios_ucode {
@@ -1100,6 +1122,8 @@ struct nvgpu_bios {
         struct bit_token *clock_token;
         struct bit_token *virt_token;
         u32 expansion_rom_offset;
+
+        u32 nvlink_config_data_offset;
 };
 
 struct nvgpu_gpu_params {
@@ -1153,8 +1177,10 @@ struct gk20a {
         struct nvgpu_falcon fecs_flcn;
         struct nvgpu_falcon gpccs_flcn;
         struct nvgpu_falcon nvdec_flcn;
+        struct nvgpu_falcon minion_flcn;
         struct clk_gk20a clk;
         struct fifo_gk20a fifo;
+        struct nvgpu_nvlink_dev nvlink;
         struct gr_gk20a gr;
         struct sim_gk20a *sim;
         struct mm_gk20a mm;