diff options
author | Deepak Nibade <dnibade@nvidia.com> | 2014-10-01 11:53:49 -0400 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-03-18 15:12:10 -0400 |
commit | f8f6b298848ed05ad83ce107ff8a4fff0b37dd2d (patch) | |
tree | 554d121fbbc47745556cd6a99c6b5d6258951b80 /drivers/gpu/nvgpu/gk20a | |
parent | 6275bbb33bb0f72cc03c7e68d8186b36c96ee854 (diff) |
gpu: nvgpu: support config of TPC FUSE dynamically
Follow steps below to config active TPC number:
echo 1 > /sys/devices/platform/host1x/gpu.0/force_idle
echo 0x1/0x2/0x3 > /sys/devices/platform/host1x/gpu.0/tpc_fs_mask
echo 0 > /sys/devices/platform/host1x/gpu.0/force_idle
where,
0x1 : disable TPC1
0x2 : disable TPC0
0x3 : both TPCs active
Also, add API set_gpc_tpc_mask to update the TPCs and call this
API after update to sysfs "tpc_fs_mask"
Once fuses are updated for new TPC settings, we need to
reconfigure GR and golden_image. Hence disable gr->sw_ready
and golden_image_initialized flags.
Also, initialize gr->tpc_count = 0 each time in
gr_gk20a_init_gr_config(), otherwise it goes on adding tpc count
Bug 1513685
Change-Id: Ib50bafef08664262f8426ac0d6cbad74b32c5909
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/552606
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a_sysfs.c | 18 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 1 |
3 files changed, 19 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 3f070a58..49038a0f 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -125,6 +125,7 @@ struct gpu_ops { | |||
125 | u32 reg_offset); | 125 | u32 reg_offset); |
126 | int (*load_ctxsw_ucode)(struct gk20a *g); | 126 | int (*load_ctxsw_ucode)(struct gk20a *g); |
127 | u32 (*get_gpc_tpc_mask)(struct gk20a *g, u32 gpc_index); | 127 | u32 (*get_gpc_tpc_mask)(struct gk20a *g, u32 gpc_index); |
128 | void (*set_gpc_tpc_mask)(struct gk20a *g, u32 gpc_index); | ||
128 | void (*free_channel_ctx)(struct channel_gk20a *c); | 129 | void (*free_channel_ctx)(struct channel_gk20a *c); |
129 | int (*alloc_obj_ctx)(struct channel_gk20a *c, | 130 | int (*alloc_obj_ctx)(struct channel_gk20a *c, |
130 | struct nvgpu_alloc_obj_ctx_args *args); | 131 | struct nvgpu_alloc_obj_ctx_args *args); |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a_sysfs.c b/drivers/gpu/nvgpu/gk20a/gk20a_sysfs.c index 1f32ac6d..42720307 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a_sysfs.c +++ b/drivers/gpu/nvgpu/gk20a/gk20a_sysfs.c | |||
@@ -607,9 +607,18 @@ static ssize_t tpc_fs_mask_store(struct device *device, | |||
607 | if (kstrtoul(buf, 10, &val) < 0) | 607 | if (kstrtoul(buf, 10, &val) < 0) |
608 | return -EINVAL; | 608 | return -EINVAL; |
609 | 609 | ||
610 | if (val) | 610 | if (val && val != g->gr.gpc_tpc_mask[0] && g->ops.gr.set_gpc_tpc_mask) { |
611 | g->gr.gpc_tpc_mask[0] = val; | 611 | g->gr.gpc_tpc_mask[0] = val; |
612 | 612 | ||
613 | g->ops.gr.set_gpc_tpc_mask(g, 0); | ||
614 | |||
615 | kfree(g->gr.ctx_vars.local_golden_image); | ||
616 | g->gr.ctx_vars.local_golden_image = NULL; | ||
617 | g->gr.ctx_vars.golden_image_initialized = false; | ||
618 | g->gr.ctx_vars.golden_image_size = 0; | ||
619 | g->gr.sw_ready = false; | ||
620 | } | ||
621 | |||
613 | return count; | 622 | return count; |
614 | } | 623 | } |
615 | 624 | ||
@@ -621,6 +630,11 @@ static ssize_t tpc_fs_mask_read(struct device *device, | |||
621 | struct gr_gk20a *gr = &g->gr; | 630 | struct gr_gk20a *gr = &g->gr; |
622 | u32 gpc_index; | 631 | u32 gpc_index; |
623 | u32 tpc_fs_mask = 0; | 632 | u32 tpc_fs_mask = 0; |
633 | int err = 0; | ||
634 | |||
635 | err = gk20a_busy(g->dev); | ||
636 | if (err) | ||
637 | return err; | ||
624 | 638 | ||
625 | for (gpc_index = 0; gpc_index < gr->gpc_count; gpc_index++) { | 639 | for (gpc_index = 0; gpc_index < gr->gpc_count; gpc_index++) { |
626 | if (g->ops.gr.get_gpc_tpc_mask) | 640 | if (g->ops.gr.get_gpc_tpc_mask) |
@@ -629,6 +643,8 @@ static ssize_t tpc_fs_mask_read(struct device *device, | |||
629 | (gr->max_tpc_per_gpc_count * gpc_index); | 643 | (gr->max_tpc_per_gpc_count * gpc_index); |
630 | } | 644 | } |
631 | 645 | ||
646 | gk20a_idle(g->dev); | ||
647 | |||
632 | return sprintf(buf, "0x%x\n", tpc_fs_mask); | 648 | return sprintf(buf, "0x%x\n", tpc_fs_mask); |
633 | } | 649 | } |
634 | 650 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index da257cd4..3cf5845c 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -3084,6 +3084,7 @@ static int gr_gk20a_init_gr_config(struct gk20a *g, struct gr_gk20a *gr) | |||
3084 | goto clean_up; | 3084 | goto clean_up; |
3085 | 3085 | ||
3086 | gr->ppc_count = 0; | 3086 | gr->ppc_count = 0; |
3087 | gr->tpc_count = 0; | ||
3087 | for (gpc_index = 0; gpc_index < gr->gpc_count; gpc_index++) { | 3088 | for (gpc_index = 0; gpc_index < gr->gpc_count; gpc_index++) { |
3088 | tmp = gk20a_readl(g, gr_gpc0_fs_gpc_r()); | 3089 | tmp = gk20a_readl(g, gr_gpc0_fs_gpc_r()); |
3089 | 3090 | ||