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author | Terje Bergstrom <tbergstrom@nvidia.com> | 2014-11-03 03:40:02 -0500 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-03-18 15:11:59 -0400 |
commit | f82d6e9d190449b06066eff1a01700e8387eb7c2 (patch) | |
tree | ca11319c970f87cf4efd2b869eb453f7664546ba /drivers/gpu/nvgpu/gk20a | |
parent | 7784fb18a3e9b86ea86c2eff756443c005dd3e32 (diff) |
gpu: nvgpu: Regenerate HW headers
Regenerate HW headers after adding SM debugger registers.
Change-Id: Icc47c11f8e9ff52c0cf1f3a54233fb781c2c2b67
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h | 28 |
2 files changed, 16 insertions, 14 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 63ab6c9f..f87608d1 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -7285,7 +7285,7 @@ void gk20a_resume_all_sms(struct gk20a *g) | |||
7285 | gr_gpcs_tpcs_sm_dbgr_control0_r(), dbgr_control0); | 7285 | gr_gpcs_tpcs_sm_dbgr_control0_r(), dbgr_control0); |
7286 | 7286 | ||
7287 | /* Run trigger */ | 7287 | /* Run trigger */ |
7288 | dbgr_control0 |= gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_enable_f(); | 7288 | dbgr_control0 |= gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f(); |
7289 | gk20a_writel(g, | 7289 | gk20a_writel(g, |
7290 | gr_gpcs_tpcs_sm_dbgr_control0_r(), dbgr_control0); | 7290 | gr_gpcs_tpcs_sm_dbgr_control0_r(), dbgr_control0); |
7291 | } | 7291 | } |
diff --git a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h index 65a3072c..3b16df58 100644 --- a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h | |||
@@ -2812,7 +2812,7 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void) | |||
2812 | } | 2812 | } |
2813 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f(void) | 2813 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f(void) |
2814 | { | 2814 | { |
2815 | return 0x00000000; | 2815 | return 0x0; |
2816 | } | 2816 | } |
2817 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void) | 2817 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void) |
2818 | { | 2818 | { |
@@ -3234,38 +3234,40 @@ static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_r(void) | |||
3234 | { | 3234 | { |
3235 | return 0x00419e10; | 3235 | return 0x00419e10; |
3236 | } | 3236 | } |
3237 | 3237 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(u32 v) | |
3238 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_r_debugger_mode_v(u32 r) | ||
3239 | { | 3238 | { |
3240 | return (r >> 0) & 0x1; | 3239 | return (v & 0x1) << 0; |
3241 | } | 3240 | } |
3242 | 3241 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_v(void) | |
3243 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(u32 r) | ||
3244 | { | 3242 | { |
3245 | return (r >> 31) & 0x1; | 3243 | return 0x00000001; |
3246 | } | 3244 | } |
3247 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m(void) | 3245 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m(void) |
3248 | { | 3246 | { |
3249 | return 0x1 << 31; | 3247 | return 0x1 << 31; |
3250 | } | 3248 | } |
3249 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(u32 r) | ||
3250 | { | ||
3251 | return (r >> 31) & 0x1; | ||
3252 | } | ||
3251 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_enable_f(void) | 3253 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_enable_f(void) |
3252 | { | 3254 | { |
3253 | return 0x80000000; | 3255 | return 0x80000000; |
3254 | } | 3256 | } |
3255 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_v(u32 r) | 3257 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f(void) |
3256 | { | 3258 | { |
3257 | return (r >> 30) & 0x1; | 3259 | return 0x0; |
3258 | } | 3260 | } |
3259 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void) | 3261 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void) |
3260 | { | 3262 | { |
3261 | return 0x1 << 30; | 3263 | return 0x1 << 30; |
3262 | } | 3264 | } |
3263 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_enable_f(void) | 3265 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_v(u32 r) |
3264 | { | 3266 | { |
3265 | return 0x40000000; | 3267 | return (r >> 30) & 0x1; |
3266 | } | 3268 | } |
3267 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_f(void) | 3269 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f(void) |
3268 | { | 3270 | { |
3269 | return 0x1; | 3271 | return 0x40000000; |
3270 | } | 3272 | } |
3271 | #endif | 3273 | #endif |