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| author | Alex Frid <afrid@nvidia.com> | 2014-10-01 19:24:58 -0400 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-03-18 15:11:34 -0400 |
| commit | f65d2dde977147801a283d0eebe1f7dcc917f2ff (patch) | |
| tree | 8e938bb26569bacf5808129d4d6992772e9b1b84 /drivers/gpu/nvgpu/gk20a | |
| parent | 2d0bcfa3318c276dba5100510e59c5c2fa62957f (diff) | |
gpu: nvgpu: Change quantize order in GPCPLL NA mode
When calculating fractional divider in GPCPLL NA mode quantize voltage
before (used to do it after) applying DFS_COEFF, to follow h/w order.
Bug 1555318
Change-Id: I37be2bc73cd1f849695b94acc4ff21caf26e8b97
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/552741
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
0 files changed, 0 insertions, 0 deletions