gpu: nvgpu: Fold T19x code back to main code paths

Lots of code paths were split to T19x specific code paths and structs
due to split repository. Now that repositories are merged, fold all of
them back to main code paths and structs and remove the T19x specific
Kconfig flag.

Change-Id: Id0d17a5f0610fc0b49f51ab6664e716dc8b222b6
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1640606
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

10 files changed, 63 insertions, 78 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
index 371793ef..2949c426 100644
--- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
@@ -1,7 +1,7 @@
 /*
  * GK20A Graphics channel
  *
- * Copyright (c) 2011-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -700,10 +700,8 @@ struct channel_gk20a *gk20a_open_new_channel(struct gk20a *g,
         ch->has_timedout = false;
         ch->wdt_enabled = true;
         ch->obj_class = 0;
-#ifdef CONFIG_TEGRA_19x_GPU
-        memset(&ch->t19x, 0, sizeof(struct channel_t19x));
-#endif
-
+        ch->subctx_id = 0;
+        ch->runqueue_sel = 0;
 
         /* The channel is *not* runnable at this point. It still needs to have
          * an address space bound and allocate a gpfifo and grctx. */
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h
index 29fa302f..db1404a3 100644
--- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h
@@ -1,7 +1,7 @@
 /*
  * GK20A graphics channel
  *
- * Copyright (c) 2011-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -40,9 +40,6 @@ struct fifo_profile_gk20a;
 #include "mm_gk20a.h"
 #include "gr_gk20a.h"
 #include "fence_gk20a.h"
-#ifdef CONFIG_TEGRA_19x_GPU
-#include "channel_t19x.h"
-#endif
 
 /* Flags to be passed to gk20a_channel_alloc_gpfifo() */
 #define NVGPU_GPFIFO_FLAGS_SUPPORT_VPR                  (1 << 0)
@@ -237,9 +234,8 @@ struct channel_gk20a {
         u32 runlist_id;
 
         bool is_privileged_channel;
-#ifdef CONFIG_TEGRA_19x_GPU
-        struct channel_t19x t19x;
-#endif
+        u32 subctx_id;
+        u32 runqueue_sel;
 
         struct ctx_header_desc ctx_header;
 
diff --git a/drivers/gpu/nvgpu/gk20a/ecc_gk20a.h b/drivers/gpu/nvgpu/gk20a/ecc_gk20a.h
index 57eec1e0..fba8ba7d 100644
--- a/drivers/gpu/nvgpu/gk20a/ecc_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/ecc_gk20a.h
@@ -1,7 +1,7 @@
 /*
  * GK20A ECC
  *
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -33,10 +33,6 @@ struct gk20a_ecc_stat {
 #endif
 };
 
-#ifdef CONFIG_TEGRA_19x_GPU
-#include "ecc_t19x.h"
-#endif
-
 struct ecc_gk20a {
         /* Stats per engine */
         struct {
@@ -56,24 +52,44 @@ struct ecc_gk20a {
                 struct gk20a_ecc_stat tex_unique_sec_pipe1_count;
                 struct gk20a_ecc_stat tex_unique_ded_pipe1_count;
 
-#ifdef CONFIG_TEGRA_19x_GPU
-                struct ecc_gr_t19x t19x;
-#endif
+                struct gk20a_ecc_stat sm_l1_tag_corrected_err_count;
+                struct gk20a_ecc_stat sm_l1_tag_uncorrected_err_count;
+                struct gk20a_ecc_stat sm_cbu_corrected_err_count;
+                struct gk20a_ecc_stat sm_cbu_uncorrected_err_count;
+                struct gk20a_ecc_stat sm_l1_data_corrected_err_count;
+                struct gk20a_ecc_stat sm_l1_data_uncorrected_err_count;
+                struct gk20a_ecc_stat sm_icache_corrected_err_count;
+                struct gk20a_ecc_stat sm_icache_uncorrected_err_count;
+                struct gk20a_ecc_stat gcc_l15_corrected_err_count;
+                struct gk20a_ecc_stat gcc_l15_uncorrected_err_count;
+                struct gk20a_ecc_stat fecs_corrected_err_count;
+                struct gk20a_ecc_stat fecs_uncorrected_err_count;
+                struct gk20a_ecc_stat gpccs_corrected_err_count;
+                struct gk20a_ecc_stat gpccs_uncorrected_err_count;
+                struct gk20a_ecc_stat mmu_l1tlb_corrected_err_count;
+                struct gk20a_ecc_stat mmu_l1tlb_uncorrected_err_count;
         } gr;
 
         struct {
                 struct gk20a_ecc_stat l2_sec_count;
                 struct gk20a_ecc_stat l2_ded_count;
-#ifdef CONFIG_TEGRA_19x_GPU
-                struct ecc_ltc_t19x t19x;
-#endif
+                struct gk20a_ecc_stat l2_cache_corrected_err_count;
+                struct gk20a_ecc_stat l2_cache_uncorrected_err_count;
         } ltc;
 
         struct {
-#ifdef CONFIG_TEGRA_19x_GPU
-                struct ecc_eng_t19x t19x;
-#endif
-        } eng;
+                struct gk20a_ecc_stat mmu_l2tlb_corrected_err_count;
+                struct gk20a_ecc_stat mmu_l2tlb_uncorrected_err_count;
+                struct gk20a_ecc_stat mmu_hubtlb_corrected_err_count;
+                struct gk20a_ecc_stat mmu_hubtlb_uncorrected_err_count;
+                struct gk20a_ecc_stat mmu_fillunit_corrected_err_count;
+                struct gk20a_ecc_stat mmu_fillunit_uncorrected_err_count;
+        } fb;
+
+        struct {
+                struct gk20a_ecc_stat pmu_corrected_err_count;
+                struct gk20a_ecc_stat pmu_uncorrected_err_count;
+        } pmu;
 
 };
 
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
index af0630d2..a925b1e2 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
@@ -1,9 +1,7 @@
 /*
- * drivers/video/tegra/host/gk20a/fifo_gk20a.h
- *
  * GK20A graphics fifo (gr host)
  *
- * Copyright (c) 2011-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -29,10 +27,6 @@
 #include "channel_gk20a.h"
 #include "tsg_gk20a.h"
 
-#ifdef CONFIG_TEGRA_19x_GPU
-#include "fifo_t19x.h"
-#endif
-
 #include <nvgpu/kref.h>
 
 struct gk20a_debug_output;
@@ -213,9 +207,7 @@ struct fifo_gk20a {
         bool deferred_reset_pending;
         struct nvgpu_mutex deferred_reset_mutex;
 
-#ifdef CONFIG_TEGRA_19x_GPU
-        struct fifo_t19x t19x;
-#endif
+        u32 max_subctx_count;
         u32 channel_base;
 };
 
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c
index c967b69b..b4886e31 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.c
@@ -1,7 +1,7 @@
 /*
  * GK20A Graphics
  *
- * Copyright (c) 2011-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -48,10 +48,6 @@
 #include "bus_gk20a.h"
 #include "pstate/pstate.h"
 
-#ifdef CONFIG_TEGRA_19x_GPU
-#include "nvgpu_gpuid_t19x.h"
-#endif
-
 void __nvgpu_check_gpu_state(struct gk20a *g)
 {
         u32 boot_0 = 0xffffffff;
@@ -127,7 +123,7 @@ int gk20a_prepare_poweroff(struct gk20a *g)
 int gk20a_finalize_poweron(struct gk20a *g)
 {
         int err;
-#if defined(CONFIG_TEGRA_GK20A_NVHOST) && defined(CONFIG_TEGRA_19x_GPU)
+#if defined(CONFIG_TEGRA_GK20A_NVHOST)
         u32 nr_pages;
 #endif
 
@@ -319,7 +315,7 @@ int gk20a_finalize_poweron(struct gk20a *g)
                 }
         }
 
-#if defined(CONFIG_TEGRA_GK20A_NVHOST) && defined(CONFIG_TEGRA_19x_GPU)
+#if defined(CONFIG_TEGRA_GK20A_NVHOST)
         if (gk20a_platform_has_syncpoints(g) && g->syncpt_unit_size) {
                 if (!nvgpu_mem_is_valid(&g->syncpt_mem)) {
                         nr_pages = DIV_ROUND_UP(g->syncpt_unit_size, PAGE_SIZE);
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 50f827a9..cc62865c 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -1342,7 +1342,7 @@ struct gk20a {
 
         u64 dma_memory_used;
 
-#if defined(CONFIG_TEGRA_GK20A_NVHOST) && defined(CONFIG_TEGRA_19x_GPU)
+#if defined(CONFIG_TEGRA_GK20A_NVHOST)
         u64             syncpt_unit_base;
         size_t          syncpt_unit_size;
         u32             syncpt_size;
@@ -1479,6 +1479,8 @@ int gk20a_wait_for_idle(struct gk20a *g);
 #define NVGPU_GPUID_GP10B   0x0000013B
 #define NVGPU_GPUID_GP104   0x00000134
 #define NVGPU_GPUID_GP106   0x00000136
+#define NVGPU_GPUID_GV11B   0x0000015B
+#define NVGPU_GPUID_GV100   0x00000140
 
 int gk20a_init_gpu_characteristics(struct gk20a *g);
 
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
index 6cc15c94..d1c32c03 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
@@ -24,10 +24,6 @@
 #ifndef GR_GK20A_H
 #define GR_GK20A_H
 
-#ifdef CONFIG_TEGRA_19x_GPU
-#include "gr_t19x.h"
-#endif
-
 #include "gr_ctx_gk20a.h"
 #include "mm_gk20a.h"
 
@@ -199,6 +195,12 @@ struct zbc_depth_table {
         u32 ref_cnt;
 };
 
+struct zbc_s_table {
+        u32 stencil;
+        u32 format;
+        u32 ref_cnt;
+};
+
 struct zbc_entry {
         u32 color_ds[GK20A_ZBC_COLOR_VALUE_SIZE];
         u32 color_l2[GK20A_ZBC_COLOR_VALUE_SIZE];
@@ -393,20 +395,14 @@ struct gr_gk20a {
         struct nvgpu_mutex zbc_lock;
         struct zbc_color_table zbc_col_tbl[GK20A_ZBC_TABLE_SIZE];
         struct zbc_depth_table zbc_dep_tbl[GK20A_ZBC_TABLE_SIZE];
-#ifdef CONFIG_TEGRA_19x_GPU
         struct zbc_s_table zbc_s_tbl[GK20A_ZBC_TABLE_SIZE];
-#endif
         s32 max_default_color_index;
         s32 max_default_depth_index;
-#ifdef CONFIG_TEGRA_19x_GPU
         s32 max_default_s_index;
-#endif
 
         u32 max_used_color_index;
         u32 max_used_depth_index;
-#ifdef CONFIG_TEGRA_19x_GPU
         u32 max_used_s_index;
-#endif
 
 #define GR_CHANNEL_MAP_TLB_SIZE         2 /* must of power of 2 */
         struct gr_channel_map_tlb_entry chid_tlb[GR_CHANNEL_MAP_TLB_SIZE];
diff --git a/drivers/gpu/nvgpu/gk20a/hal.c b/drivers/gpu/nvgpu/gk20a/hal.c
index d24d4bc5..ec6816c6 100644
--- a/drivers/gpu/nvgpu/gk20a/hal.c
+++ b/drivers/gpu/nvgpu/gk20a/hal.c
@@ -1,7 +1,7 @@
 /*
  * NVIDIA GPU HAL interface.
  *
- * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -27,10 +27,8 @@
 #include "gm20b/hal_gm20b.h"
 #include "gp10b/hal_gp10b.h"
 #include "gp106/hal_gp106.h"
-
-#ifdef CONFIG_TEGRA_19x_GPU
-#include "nvgpu_gpuid_t19x.h"
-#endif
+#include "gv100/hal_gv100.h"
+#include "gv11b/hal_gv11b.h"
 
 #include <nvgpu/log.h>
 
@@ -53,17 +51,15 @@ int gpu_init_hal(struct gk20a *g)
                 if (gp106_init_hal(g))
                         return -ENODEV;
                 break;
-#ifdef CONFIG_TEGRA_19x_GPU
-        case TEGRA_19x_GPUID:
-                if (TEGRA_19x_GPUID_HAL(g))
+        case NVGPU_GPUID_GV11B:
+                if (gv11b_init_hal(g))
                         return -ENODEV;
                 break;
-        case BIGGPU_19x_GPUID:
-                if (BIGGPU_19x_GPUID_HAL(g))
+        case NVGPU_GPUID_GV100:
+                if (gv100_init_hal(g))
                         return -ENODEV;
                 break;
 
-#endif
         default:
                 nvgpu_err(g, "no support for %x", ver);
                 return -ENODEV;
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
index 9c2f72fb..603d25fe 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
@@ -1,7 +1,7 @@
 /*
  * GK20A PMU (aka. gPMU outside gk20a context)
  *
- * Copyright (c) 2011-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -39,10 +39,6 @@
 #include <nvgpu/hw/gk20a/hw_pwr_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_top_gk20a.h>
 
-#ifdef CONFIG_TEGRA_19x_GPU
-#include "nvgpu_gpuid_t19x.h"
-#endif
-
 #define gk20a_dbg_pmu(fmt, arg...) \
         gk20a_dbg(gpu_dbg_pmu, fmt, ##arg)
 
diff --git a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h
index 2168cb4f..438002e4 100644
--- a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -28,9 +28,6 @@
 
 #include "gr_gk20a.h"
 
-#ifdef CONFIG_TEGRA_19x_GPU
-#include "tsg_t19x.h"
-#endif
 #define NVGPU_INVALID_TSG_ID (-1)
 
 struct channel_gk20a;
@@ -68,9 +65,9 @@ struct tsg_gk20a {
         u32 runlist_id;
         pid_t tgid;
         struct nvgpu_mem *eng_method_buffers;
-#ifdef CONFIG_TEGRA_19x_GPU
-        struct tsg_t19x t19x;
-#endif
+        u32  num_active_tpcs;
+        u8   tpc_pg_enabled;
+        bool tpc_num_initialized;
 
         struct nvgpu_gr_ctx gr_ctx;
 };