gpu: nvgpu: Move SM_MASK_TYPE setting to TSG level

Moved the SM_MASK_TYPE variable from GR to
TSG struct. SM error registers are context based.

In dbg_session IOCTL to SET_SM_MASK_TYPE, kernel
code iterate the TSG associated with first channel
and set the mask_type to that context.

Bug 200412641

Change-Id: Ic91944037ad2447f403b4803d5266ae6250ba4c9
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1809322
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

4 files changed, 6 insertions, 11 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.h b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.h
index 4d3c4d74..50002557 100644
--- a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.h
@@ -72,12 +72,6 @@ struct dbg_session_gk20a {
         bool broadcast_stop_trigger;
 
         struct nvgpu_mutex ioctl_lock;
-
-        /*
-         * sm set exception type mask flag, to check whether
-         * exception type mask is requested or not.
-         */
-        bool is_sm_exception_type_mask_set;
 };
 
 struct dbg_session_data {
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
index 0d32cca3..303e1f53 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
@@ -420,11 +420,6 @@ struct gr_gk20a {
         u32 no_of_sm;
         struct sm_info *sm_to_cluster;
 
-#define NVGPU_SM_EXCEPTION_TYPE_MASK_NONE               (0x0U)
-#define NVGPU_SM_EXCEPTION_TYPE_MASK_FATAL              (0x1U << 0)
-        u32 sm_exception_mask_type;
-        u32 sm_exception_mask_refcount;
-
 #if defined(CONFIG_GK20A_CYCLE_STATS)
         struct nvgpu_mutex                      cs_lock;
         struct gk20a_cs_snapshot        *cs_data;
diff --git a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c
index 624ee1d7..506d4330 100644
--- a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c
@@ -304,6 +304,7 @@ struct tsg_gk20a *gk20a_tsg_open(struct gk20a *g, pid_t pid)
         tsg->timeslice_scale = 0;
         tsg->runlist_id = ~0;
         tsg->tgid = pid;
+        tsg->sm_exception_mask_type = NVGPU_SM_EXCEPTION_TYPE_MASK_NONE;
 
         if (g->ops.fifo.init_eng_method_buffers)
                 g->ops.fifo.init_eng_method_buffers(g, tsg);
@@ -373,6 +374,7 @@ void gk20a_tsg_release(struct nvgpu_ref *ref)
         release_used_tsg(&g->fifo, tsg);
 
         tsg->runlist_id = ~0;
+        tsg->sm_exception_mask_type = NVGPU_SM_EXCEPTION_TYPE_MASK_NONE;
 
         nvgpu_log(g, gpu_dbg_fn, "tsg released %d\n", tsg->tsgid);
 }
diff --git a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h
index 67ccb9f5..1e3be553 100644
--- a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h
@@ -78,6 +78,10 @@ struct tsg_gk20a {
         bool in_use;
 
         struct nvgpu_tsg_sm_error_state *sm_error_states;
+
+#define NVGPU_SM_EXCEPTION_TYPE_MASK_NONE               (0x0U)
+#define NVGPU_SM_EXCEPTION_TYPE_MASK_FATAL              (0x1U << 0)
+        u32 sm_exception_mask_type;
 };
 
 int gk20a_enable_tsg(struct tsg_gk20a *tsg);