gpu: nvgpu: Move setting priv interrupt to priv_ring

Registers to set priv interrupts are in priv_ring, but the code was
in bus HAL. Move the code and related HALs to priv_ring instead.

JIRA NVGPU-588

Change-Id: I708d11f77405dbba86586a0d1da42f65bcc1de9d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730889
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

4 files changed, 16 insertions, 3 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 77e6e759..2d304cff 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -1128,7 +1128,6 @@ struct gpu_ops {
                         u32 source_id, u32 count,
                         struct nvgpu_cpu_time_correlation_sample *);
                 int (*bar1_bind)(struct gk20a *g, struct nvgpu_mem *bar1_inst);
-                void (*set_ppriv_timeout_settings)(struct gk20a *g);
         } bus;
 
         struct {
@@ -1179,6 +1178,7 @@ struct gpu_ops {
         struct {
                 void (*isr)(struct gk20a *g);
                 void (*decode_error_code)(struct gk20a *g, u32 error_code);
+                void (*set_ppriv_timeout_settings)(struct gk20a *g);
         } priv_ring;
         struct {
                 int (*check_priv_security)(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 52346541..42e96715 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -4502,8 +4502,8 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g)
 
         gr_gk20a_zcull_init_hw(g, gr);
 
-        if (g->ops.bus.set_ppriv_timeout_settings)
-                g->ops.bus.set_ppriv_timeout_settings(g);
+        if (g->ops.priv_ring.set_ppriv_timeout_settings)
+                g->ops.priv_ring.set_ppriv_timeout_settings(g);
 
         /* enable fifo access */
         gk20a_writel(g, gr_gpfifo_ctl_r(),
diff --git a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c
index dea42b55..adbaf94f 100644
--- a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c
@@ -32,6 +32,7 @@
 #include <nvgpu/hw/gk20a/hw_pri_ringmaster_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_pri_ringstation_sys_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_pri_ringstation_gpc_gk20a.h>
+#include <nvgpu/hw/gk20a/hw_pri_ringstation_fbp_gk20a.h>
 
 void gk20a_enable_priv_ring(struct gk20a *g)
 {
@@ -103,3 +104,14 @@ void gk20a_priv_ring_isr(struct gk20a *g)
         if (retry == 0 && cmd != pri_ringmaster_command_cmd_no_cmd_v())
                 nvgpu_warn(g, "priv ringmaster intr ack too many retries");
 }
+
+void gk20a_priv_set_timeout_settings(struct gk20a *g)
+{
+        /*
+         * Bug 1340570: increase the clock timeout to avoid potential
+         * operation failure at high gpcclk rate. Default values are 0x400.
+         */
+        nvgpu_writel(g, pri_ringstation_sys_master_config_r(0x15), 0x800);
+        nvgpu_writel(g, pri_ringstation_gpc_master_config_r(0xa), 0x800);
+        nvgpu_writel(g, pri_ringstation_fbp_master_config_r(0x8), 0x800);
+}
diff --git a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.h b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.h
index ef564eeb..98040624 100644
--- a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.h
@@ -28,5 +28,6 @@ struct gpu_ops;
 
 void gk20a_priv_ring_isr(struct gk20a *g);
 void gk20a_enable_priv_ring(struct gk20a *g);
+void gk20a_priv_set_timeout_settings(struct gk20a *g);
 
 #endif /*__PRIV_RING_GK20A_H__*/