diff options
author | Deepak Goyal <dgoyal@nvidia.com> | 2016-11-23 23:42:02 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-01-18 19:46:27 -0500 |
commit | eba4aba00c54485e76e8d8adf5430abd9d10fe79 (patch) | |
tree | 28d2f3dfafc30bd00772213931eddb2fb1d85daf /drivers/gpu/nvgpu/gk20a | |
parent | 911dcedb489ebef5758e5533f73e8653cc7770b7 (diff) |
nvgpu: pmu: Add support for new PMU ucode.
-GV11B PMU ucode is added in nvgpu supported
ucodes.
-PMU INIT msg structure(v4) is added
JIRA GV11B-30
Change-Id: Ifced87b1ca2692c277ae11f562cb36b328da3fe4
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: http://git-master/r/1259274
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 151 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | 18 |
2 files changed, 169 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index 9e722889..c9eb25fe 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -597,11 +597,24 @@ static void pmu_allocation_set_dmem_offset_v0(struct pmu_gk20a *pmu, | |||
597 | pmu_a_ptr->alloc.dmem.offset = offset; | 597 | pmu_a_ptr->alloc.dmem.offset = offset; |
598 | } | 598 | } |
599 | 599 | ||
600 | static void *get_pmu_msg_pmu_init_msg_ptr_v4(struct pmu_init_msg *init) | ||
601 | { | ||
602 | return (void *)(&(init->pmu_init_v4)); | ||
603 | } | ||
604 | |||
600 | static void *get_pmu_msg_pmu_init_msg_ptr_v3(struct pmu_init_msg *init) | 605 | static void *get_pmu_msg_pmu_init_msg_ptr_v3(struct pmu_init_msg *init) |
601 | { | 606 | { |
602 | return (void *)(&(init->pmu_init_v3)); | 607 | return (void *)(&(init->pmu_init_v3)); |
603 | } | 608 | } |
604 | 609 | ||
610 | static u16 get_pmu_init_msg_pmu_sw_mg_off_v4(union pmu_init_msg_pmu *init_msg) | ||
611 | { | ||
612 | struct pmu_init_msg_pmu_v4 *init = | ||
613 | (struct pmu_init_msg_pmu_v4 *)(&init_msg->v4); | ||
614 | |||
615 | return init->sw_managed_area_offset; | ||
616 | } | ||
617 | |||
605 | static u16 get_pmu_init_msg_pmu_sw_mg_off_v3(union pmu_init_msg_pmu *init_msg) | 618 | static u16 get_pmu_init_msg_pmu_sw_mg_off_v3(union pmu_init_msg_pmu *init_msg) |
606 | { | 619 | { |
607 | struct pmu_init_msg_pmu_v3 *init = | 620 | struct pmu_init_msg_pmu_v3 *init = |
@@ -610,6 +623,14 @@ static u16 get_pmu_init_msg_pmu_sw_mg_off_v3(union pmu_init_msg_pmu *init_msg) | |||
610 | return init->sw_managed_area_offset; | 623 | return init->sw_managed_area_offset; |
611 | } | 624 | } |
612 | 625 | ||
626 | static u16 get_pmu_init_msg_pmu_sw_mg_size_v4(union pmu_init_msg_pmu *init_msg) | ||
627 | { | ||
628 | struct pmu_init_msg_pmu_v4 *init = | ||
629 | (struct pmu_init_msg_pmu_v4 *)(&init_msg->v4); | ||
630 | |||
631 | return init->sw_managed_area_size; | ||
632 | } | ||
633 | |||
613 | static u16 get_pmu_init_msg_pmu_sw_mg_size_v3(union pmu_init_msg_pmu *init_msg) | 634 | static u16 get_pmu_init_msg_pmu_sw_mg_size_v3(union pmu_init_msg_pmu *init_msg) |
614 | { | 635 | { |
615 | struct pmu_init_msg_pmu_v3 *init = | 636 | struct pmu_init_msg_pmu_v3 *init = |
@@ -1156,6 +1177,31 @@ static void get_pmu_init_msg_pmu_queue_params_v2(struct pmu_queue *queue, | |||
1156 | queue->size = init->queue_info[id].size; | 1177 | queue->size = init->queue_info[id].size; |
1157 | } | 1178 | } |
1158 | 1179 | ||
1180 | static void get_pmu_init_msg_pmu_queue_params_v4(struct pmu_queue *queue, | ||
1181 | u32 id, void *pmu_init_msg) | ||
1182 | { | ||
1183 | struct pmu_init_msg_pmu_v4 *init = pmu_init_msg; | ||
1184 | u32 current_ptr = 0; | ||
1185 | u8 i; | ||
1186 | u8 tmp_id = id; | ||
1187 | |||
1188 | if (tmp_id == PMU_COMMAND_QUEUE_HPQ) | ||
1189 | tmp_id = PMU_QUEUE_HPQ_IDX_FOR_V3; | ||
1190 | else if (tmp_id == PMU_COMMAND_QUEUE_LPQ) | ||
1191 | tmp_id = PMU_QUEUE_LPQ_IDX_FOR_V3; | ||
1192 | else if (tmp_id == PMU_MESSAGE_QUEUE) | ||
1193 | tmp_id = PMU_QUEUE_MSG_IDX_FOR_V3; | ||
1194 | else | ||
1195 | return; | ||
1196 | |||
1197 | queue->index = init->queue_index[tmp_id]; | ||
1198 | queue->size = init->queue_size[tmp_id]; | ||
1199 | if (tmp_id != 0) { | ||
1200 | for (i = 0 ; i < tmp_id; i++) | ||
1201 | current_ptr += init->queue_size[i]; | ||
1202 | } | ||
1203 | queue->offset = init->queue_offset + current_ptr; | ||
1204 | } | ||
1159 | static void get_pmu_init_msg_pmu_queue_params_v3(struct pmu_queue *queue, | 1205 | static void get_pmu_init_msg_pmu_queue_params_v3(struct pmu_queue *queue, |
1160 | u32 id, void *pmu_init_msg) | 1206 | u32 id, void *pmu_init_msg) |
1161 | { | 1207 | { |
@@ -1477,6 +1523,111 @@ int gk20a_init_pmu(struct pmu_gk20a *pmu) | |||
1477 | g->ops.pmu_ver.get_pmu_seq_out_a_ptr = | 1523 | g->ops.pmu_ver.get_pmu_seq_out_a_ptr = |
1478 | get_pmu_sequence_out_alloc_ptr_v1; | 1524 | get_pmu_sequence_out_alloc_ptr_v1; |
1479 | break; | 1525 | break; |
1526 | case APP_VERSION_NC_3: | ||
1527 | g->ops.pmu_ver.pg_cmd_eng_buf_load_size = | ||
1528 | pg_cmd_eng_buf_load_size_v2; | ||
1529 | g->ops.pmu_ver.pg_cmd_eng_buf_load_set_cmd_type = | ||
1530 | pg_cmd_eng_buf_load_set_cmd_type_v2; | ||
1531 | g->ops.pmu_ver.pg_cmd_eng_buf_load_set_engine_id = | ||
1532 | pg_cmd_eng_buf_load_set_engine_id_v2; | ||
1533 | g->ops.pmu_ver.pg_cmd_eng_buf_load_set_buf_idx = | ||
1534 | pg_cmd_eng_buf_load_set_buf_idx_v2; | ||
1535 | g->ops.pmu_ver.pg_cmd_eng_buf_load_set_pad = | ||
1536 | pg_cmd_eng_buf_load_set_pad_v2; | ||
1537 | g->ops.pmu_ver.pg_cmd_eng_buf_load_set_buf_size = | ||
1538 | pg_cmd_eng_buf_load_set_buf_size_v2; | ||
1539 | g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_base = | ||
1540 | pg_cmd_eng_buf_load_set_dma_base_v2; | ||
1541 | g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_offset = | ||
1542 | pg_cmd_eng_buf_load_set_dma_offset_v2; | ||
1543 | g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_idx = | ||
1544 | pg_cmd_eng_buf_load_set_dma_idx_v2; | ||
1545 | g->ops.pmu_ver.get_perfmon_cntr_ptr = get_perfmon_cntr_ptr_v2; | ||
1546 | g->ops.pmu_ver.set_perfmon_cntr_ut = set_perfmon_cntr_ut_v2; | ||
1547 | g->ops.pmu_ver.set_perfmon_cntr_lt = set_perfmon_cntr_lt_v2; | ||
1548 | g->ops.pmu_ver.set_perfmon_cntr_valid = | ||
1549 | set_perfmon_cntr_valid_v2; | ||
1550 | g->ops.pmu_ver.set_perfmon_cntr_index = | ||
1551 | set_perfmon_cntr_index_v2; | ||
1552 | g->ops.pmu_ver.set_perfmon_cntr_group_id = | ||
1553 | set_perfmon_cntr_group_id_v2; | ||
1554 | g->ops.pmu_ver.get_perfmon_cntr_sz = pmu_perfmon_cntr_sz_v2; | ||
1555 | g->ops.pmu_ver.cmd_id_zbc_table_update = 16; | ||
1556 | g->ops.pmu_ver.get_pmu_cmdline_args_size = | ||
1557 | pmu_cmdline_size_v5; | ||
1558 | g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq = | ||
1559 | set_pmu_cmdline_args_cpufreq_v5; | ||
1560 | g->ops.pmu_ver.set_pmu_cmdline_args_secure_mode = | ||
1561 | set_pmu_cmdline_args_secure_mode_v5; | ||
1562 | g->ops.pmu_ver.set_pmu_cmdline_args_trace_size = | ||
1563 | set_pmu_cmdline_args_falctracesize_v5; | ||
1564 | g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_base = | ||
1565 | set_pmu_cmdline_args_falctracedmabase_v5; | ||
1566 | g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_idx = | ||
1567 | set_pmu_cmdline_args_falctracedmaidx_v5; | ||
1568 | g->ops.pmu_ver.get_pmu_cmdline_args_ptr = | ||
1569 | get_pmu_cmdline_args_ptr_v5; | ||
1570 | g->ops.pmu_ver.get_pmu_allocation_struct_size = | ||
1571 | get_pmu_allocation_size_v3; | ||
1572 | g->ops.pmu_ver.set_pmu_allocation_ptr = | ||
1573 | set_pmu_allocation_ptr_v3; | ||
1574 | g->ops.pmu_ver.pmu_allocation_set_dmem_size = | ||
1575 | pmu_allocation_set_dmem_size_v3; | ||
1576 | g->ops.pmu_ver.pmu_allocation_get_dmem_size = | ||
1577 | pmu_allocation_get_dmem_size_v3; | ||
1578 | g->ops.pmu_ver.pmu_allocation_get_dmem_offset = | ||
1579 | pmu_allocation_get_dmem_offset_v3; | ||
1580 | g->ops.pmu_ver.pmu_allocation_get_dmem_offset_addr = | ||
1581 | pmu_allocation_get_dmem_offset_addr_v3; | ||
1582 | g->ops.pmu_ver.pmu_allocation_set_dmem_offset = | ||
1583 | pmu_allocation_set_dmem_offset_v3; | ||
1584 | g->ops.pmu_ver.pmu_allocation_get_fb_addr = | ||
1585 | pmu_allocation_get_fb_addr_v3; | ||
1586 | g->ops.pmu_ver.pmu_allocation_get_fb_size = | ||
1587 | pmu_allocation_get_fb_size_v3; | ||
1588 | g->ops.pmu_ver.get_pmu_init_msg_pmu_queue_params = | ||
1589 | get_pmu_init_msg_pmu_queue_params_v4; | ||
1590 | g->ops.pmu_ver.get_pmu_msg_pmu_init_msg_ptr = | ||
1591 | get_pmu_msg_pmu_init_msg_ptr_v4; | ||
1592 | g->ops.pmu_ver.get_pmu_init_msg_pmu_sw_mg_off = | ||
1593 | get_pmu_init_msg_pmu_sw_mg_off_v4; | ||
1594 | g->ops.pmu_ver.get_pmu_init_msg_pmu_sw_mg_size = | ||
1595 | get_pmu_init_msg_pmu_sw_mg_size_v4; | ||
1596 | g->ops.pmu_ver.get_pmu_perfmon_cmd_start_size = | ||
1597 | get_pmu_perfmon_cmd_start_size_v3; | ||
1598 | g->ops.pmu_ver.get_perfmon_cmd_start_offsetofvar = | ||
1599 | get_perfmon_cmd_start_offsetofvar_v3; | ||
1600 | g->ops.pmu_ver.perfmon_start_set_cmd_type = | ||
1601 | perfmon_start_set_cmd_type_v3; | ||
1602 | g->ops.pmu_ver.perfmon_start_set_group_id = | ||
1603 | perfmon_start_set_group_id_v3; | ||
1604 | g->ops.pmu_ver.perfmon_start_set_state_id = | ||
1605 | perfmon_start_set_state_id_v3; | ||
1606 | g->ops.pmu_ver.perfmon_start_set_flags = | ||
1607 | perfmon_start_set_flags_v3; | ||
1608 | g->ops.pmu_ver.perfmon_start_get_flags = | ||
1609 | perfmon_start_get_flags_v3; | ||
1610 | g->ops.pmu_ver.get_pmu_perfmon_cmd_init_size = | ||
1611 | get_pmu_perfmon_cmd_init_size_v3; | ||
1612 | g->ops.pmu_ver.get_perfmon_cmd_init_offsetofvar = | ||
1613 | get_perfmon_cmd_init_offsetofvar_v3; | ||
1614 | g->ops.pmu_ver.perfmon_cmd_init_set_sample_buffer = | ||
1615 | perfmon_cmd_init_set_sample_buffer_v3; | ||
1616 | g->ops.pmu_ver.perfmon_cmd_init_set_dec_cnt = | ||
1617 | perfmon_cmd_init_set_dec_cnt_v3; | ||
1618 | g->ops.pmu_ver.perfmon_cmd_init_set_base_cnt_id = | ||
1619 | perfmon_cmd_init_set_base_cnt_id_v3; | ||
1620 | g->ops.pmu_ver.perfmon_cmd_init_set_samp_period_us = | ||
1621 | perfmon_cmd_init_set_samp_period_us_v3; | ||
1622 | g->ops.pmu_ver.perfmon_cmd_init_set_num_cnt = | ||
1623 | perfmon_cmd_init_set_num_cnt_v3; | ||
1624 | g->ops.pmu_ver.perfmon_cmd_init_set_mov_avg = | ||
1625 | perfmon_cmd_init_set_mov_avg_v3; | ||
1626 | g->ops.pmu_ver.get_pmu_seq_in_a_ptr = | ||
1627 | get_pmu_sequence_in_alloc_ptr_v3; | ||
1628 | g->ops.pmu_ver.get_pmu_seq_out_a_ptr = | ||
1629 | get_pmu_sequence_out_alloc_ptr_v3; | ||
1630 | break; | ||
1480 | case APP_VERSION_GM206: | 1631 | case APP_VERSION_GM206: |
1481 | case APP_VERSION_NV_GPU: | 1632 | case APP_VERSION_NV_GPU: |
1482 | case APP_VERSION_NV_GPU_1: | 1633 | case APP_VERSION_NV_GPU_1: |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h index daa050af..b6f2e013 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | |||
@@ -38,6 +38,7 @@ | |||
38 | 38 | ||
39 | #define ZBC_MASK(i) (~(~(0) << ((i)+1)) & 0xfffe) | 39 | #define ZBC_MASK(i) (~(~(0) << ((i)+1)) & 0xfffe) |
40 | 40 | ||
41 | #define APP_VERSION_NC_3 21548462 | ||
41 | #define APP_VERSION_NC_2 20429989 | 42 | #define APP_VERSION_NC_2 20429989 |
42 | #define APP_VERSION_NC_1 20313802 | 43 | #define APP_VERSION_NC_1 20313802 |
43 | #define APP_VERSION_NC_0 20360931 | 44 | #define APP_VERSION_NC_0 20360931 |
@@ -264,6 +265,7 @@ struct pmu_init_msg_pmu_v2 { | |||
264 | u8 dummy[18]; | 265 | u8 dummy[18]; |
265 | }; | 266 | }; |
266 | 267 | ||
268 | #define PMU_QUEUE_COUNT_FOR_V4 5 | ||
267 | #define PMU_QUEUE_COUNT_FOR_V3 3 | 269 | #define PMU_QUEUE_COUNT_FOR_V3 3 |
268 | #define PMU_QUEUE_HPQ_IDX_FOR_V3 0 | 270 | #define PMU_QUEUE_HPQ_IDX_FOR_V3 0 |
269 | #define PMU_QUEUE_LPQ_IDX_FOR_V3 1 | 271 | #define PMU_QUEUE_LPQ_IDX_FOR_V3 1 |
@@ -282,11 +284,26 @@ struct pmu_init_msg_pmu_v3 { | |||
282 | u8 dummy[18]; | 284 | u8 dummy[18]; |
283 | }; | 285 | }; |
284 | 286 | ||
287 | struct pmu_init_msg_pmu_v4 { | ||
288 | u8 msg_type; | ||
289 | u8 queue_index[PMU_QUEUE_COUNT_FOR_V4]; | ||
290 | u16 queue_size[PMU_QUEUE_COUNT_FOR_V4]; | ||
291 | u16 queue_offset; | ||
292 | |||
293 | u16 sw_managed_area_offset; | ||
294 | u16 sw_managed_area_size; | ||
295 | |||
296 | u16 os_debug_entry_point; | ||
297 | |||
298 | u8 dummy[18]; | ||
299 | }; | ||
300 | |||
285 | union pmu_init_msg_pmu { | 301 | union pmu_init_msg_pmu { |
286 | struct pmu_init_msg_pmu_v0 v0; | 302 | struct pmu_init_msg_pmu_v0 v0; |
287 | struct pmu_init_msg_pmu_v1 v1; | 303 | struct pmu_init_msg_pmu_v1 v1; |
288 | struct pmu_init_msg_pmu_v2 v2; | 304 | struct pmu_init_msg_pmu_v2 v2; |
289 | struct pmu_init_msg_pmu_v3 v3; | 305 | struct pmu_init_msg_pmu_v3 v3; |
306 | struct pmu_init_msg_pmu_v4 v4; | ||
290 | }; | 307 | }; |
291 | 308 | ||
292 | struct pmu_init_msg { | 309 | struct pmu_init_msg { |
@@ -296,6 +313,7 @@ struct pmu_init_msg { | |||
296 | struct pmu_init_msg_pmu_v0 pmu_init_v0; | 313 | struct pmu_init_msg_pmu_v0 pmu_init_v0; |
297 | struct pmu_init_msg_pmu_v2 pmu_init_v2; | 314 | struct pmu_init_msg_pmu_v2 pmu_init_v2; |
298 | struct pmu_init_msg_pmu_v3 pmu_init_v3; | 315 | struct pmu_init_msg_pmu_v3 pmu_init_v3; |
316 | struct pmu_init_msg_pmu_v4 pmu_init_v4; | ||
299 | }; | 317 | }; |
300 | }; | 318 | }; |
301 | 319 | ||