diff options
author | Supriya <ssharatkumar@nvidia.com> | 2014-10-27 08:01:04 -0400 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-03-18 15:11:56 -0400 |
commit | eb690cb391ca0578a2c086eff5085f16c32f651e (patch) | |
tree | eaa7ba386296c52a3ded108ca53418b5a91cf8ae /drivers/gpu/nvgpu/gk20a | |
parent | 8c6a9fd1151299697037d58f33cfa306d8ac5d87 (diff) |
gpu: nvgpu: Changes to support LS sig
Support added to send PMU and FECS signatures
to ACR ucode
Bug 200046413
Change-Id: Ie1babb640be20a697ad4d6dd18bd11161edb263c
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Signed-off-by: Supriya <ssharatkumar@nvidia.com>
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 119 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | 14 |
4 files changed, 137 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 524547e7..b07d0803 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -1998,6 +1998,8 @@ void gr_gk20a_load_ctxsw_ucode_header(struct gk20a *g, u64 addr_base, | |||
1998 | 1998 | ||
1999 | /* Write out the actual data */ | 1999 | /* Write out the actual data */ |
2000 | switch (segments->boot_signature) { | 2000 | switch (segments->boot_signature) { |
2001 | case FALCON_UCODE_SIG_T21X_FECS_WITH_RESERVED: | ||
2002 | case FALCON_UCODE_SIG_T21X_GPCCS_WITH_RESERVED: | ||
2001 | case FALCON_UCODE_SIG_T12X_FECS_WITH_RESERVED: | 2003 | case FALCON_UCODE_SIG_T12X_FECS_WITH_RESERVED: |
2002 | case FALCON_UCODE_SIG_T12X_GPCCS_WITH_RESERVED: | 2004 | case FALCON_UCODE_SIG_T12X_GPCCS_WITH_RESERVED: |
2003 | gk20a_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0); | 2005 | gk20a_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index 7db6bccf..7a4303f7 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -304,10 +304,12 @@ struct gk20a_ctxsw_ucode_segments { | |||
304 | /* sums over the ucode files as sequences of u32, computed to the | 304 | /* sums over the ucode files as sequences of u32, computed to the |
305 | * boot_signature field in the structure above */ | 305 | * boot_signature field in the structure above */ |
306 | 306 | ||
307 | #define FALCON_UCODE_SIG_T21X_FECS_WITH_RESERVED 0x9125ab5c | ||
307 | #define FALCON_UCODE_SIG_T12X_FECS_WITH_RESERVED 0x8a621f78 | 308 | #define FALCON_UCODE_SIG_T12X_FECS_WITH_RESERVED 0x8a621f78 |
308 | #define FALCON_UCODE_SIG_T12X_FECS_WITHOUT_RESERVED 0x67e5344b | 309 | #define FALCON_UCODE_SIG_T12X_FECS_WITHOUT_RESERVED 0x67e5344b |
309 | #define FALCON_UCODE_SIG_T12X_FECS_OLDER 0x56da09f | 310 | #define FALCON_UCODE_SIG_T12X_FECS_OLDER 0x56da09f |
310 | 311 | ||
312 | #define FALCON_UCODE_SIG_T21X_GPCCS_WITH_RESERVED 0x3d3d65e2 | ||
311 | #define FALCON_UCODE_SIG_T12X_GPCCS_WITH_RESERVED 0x303465d5 | 313 | #define FALCON_UCODE_SIG_T12X_GPCCS_WITH_RESERVED 0x303465d5 |
312 | #define FALCON_UCODE_SIG_T12X_GPCCS_WITHOUT_RESERVED 0x3fdd33d3 | 314 | #define FALCON_UCODE_SIG_T12X_GPCCS_WITHOUT_RESERVED 0x3fdd33d3 |
313 | #define FALCON_UCODE_SIG_T12X_GPCCS_OLDER 0x53d7877 | 315 | #define FALCON_UCODE_SIG_T12X_GPCCS_OLDER 0x53d7877 |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index 0580f19d..3fa7e53c 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -155,6 +155,37 @@ static void set_pmu_cmdline_args_falctracedmaidx_v2( | |||
155 | pmu->args_v2.falc_trace_dma_idx = idx; | 155 | pmu->args_v2.falc_trace_dma_idx = idx; |
156 | } | 156 | } |
157 | 157 | ||
158 | static u32 pmu_cmdline_size_v3(struct pmu_gk20a *pmu) | ||
159 | { | ||
160 | return sizeof(struct pmu_cmdline_args_v3); | ||
161 | } | ||
162 | |||
163 | static void set_pmu_cmdline_args_cpufreq_v3(struct pmu_gk20a *pmu, u32 freq) | ||
164 | { | ||
165 | pmu->args_v3.cpu_freq_hz = freq; | ||
166 | } | ||
167 | static void set_pmu_cmdline_args_secure_mode_v3(struct pmu_gk20a *pmu, u32 val) | ||
168 | { | ||
169 | pmu->args_v3.secure_mode = val; | ||
170 | } | ||
171 | |||
172 | static void set_pmu_cmdline_args_falctracesize_v3( | ||
173 | struct pmu_gk20a *pmu, u32 size) | ||
174 | { | ||
175 | pmu->args_v3.falc_trace_size = size; | ||
176 | } | ||
177 | |||
178 | static void set_pmu_cmdline_args_falctracedmabase_v3(struct pmu_gk20a *pmu) | ||
179 | { | ||
180 | pmu->args_v3.falc_trace_dma_base = ((u32)pmu->trace_buf.pmu_va)/0x100; | ||
181 | } | ||
182 | |||
183 | static void set_pmu_cmdline_args_falctracedmaidx_v3( | ||
184 | struct pmu_gk20a *pmu, u32 idx) | ||
185 | { | ||
186 | pmu->args_v3.falc_trace_dma_idx = idx; | ||
187 | } | ||
188 | |||
158 | static void set_pmu_cmdline_args_cpufreq_v1(struct pmu_gk20a *pmu, u32 freq) | 189 | static void set_pmu_cmdline_args_cpufreq_v1(struct pmu_gk20a *pmu, u32 freq) |
159 | { | 190 | { |
160 | pmu->args_v1.cpu_freq_hz = freq; | 191 | pmu->args_v1.cpu_freq_hz = freq; |
@@ -229,6 +260,11 @@ static void set_pmu_cmdline_args_cpufreq_v0(struct pmu_gk20a *pmu, u32 freq) | |||
229 | pmu->args_v0.cpu_freq_hz = freq; | 260 | pmu->args_v0.cpu_freq_hz = freq; |
230 | } | 261 | } |
231 | 262 | ||
263 | static void *get_pmu_cmdline_args_ptr_v3(struct pmu_gk20a *pmu) | ||
264 | { | ||
265 | return (void *)(&pmu->args_v3); | ||
266 | } | ||
267 | |||
232 | static void *get_pmu_cmdline_args_ptr_v2(struct pmu_gk20a *pmu) | 268 | static void *get_pmu_cmdline_args_ptr_v2(struct pmu_gk20a *pmu) |
233 | { | 269 | { |
234 | return (void *)(&pmu->args_v2); | 270 | return (void *)(&pmu->args_v2); |
@@ -661,6 +697,89 @@ int gk20a_init_pmu(struct pmu_gk20a *pmu) | |||
661 | pmu->remove_support = gk20a_remove_pmu_support; | 697 | pmu->remove_support = gk20a_remove_pmu_support; |
662 | 698 | ||
663 | switch (pmu->desc->app_version) { | 699 | switch (pmu->desc->app_version) { |
700 | case APP_VERSION_GM20B_4: | ||
701 | g->ops.pmu_ver.get_perfmon_cntr_ptr = get_perfmon_cntr_ptr_v2; | ||
702 | g->ops.pmu_ver.set_perfmon_cntr_ut = set_perfmon_cntr_ut_v2; | ||
703 | g->ops.pmu_ver.set_perfmon_cntr_lt = set_perfmon_cntr_lt_v2; | ||
704 | g->ops.pmu_ver.set_perfmon_cntr_valid = | ||
705 | set_perfmon_cntr_valid_v2; | ||
706 | g->ops.pmu_ver.set_perfmon_cntr_index = | ||
707 | set_perfmon_cntr_index_v2; | ||
708 | g->ops.pmu_ver.set_perfmon_cntr_group_id = | ||
709 | set_perfmon_cntr_group_id_v2; | ||
710 | g->ops.pmu_ver.get_perfmon_cntr_sz = pmu_perfmon_cntr_sz_v2; | ||
711 | g->ops.pmu_ver.cmd_id_zbc_table_update = 16; | ||
712 | g->ops.pmu_ver.get_pmu_cmdline_args_size = | ||
713 | pmu_cmdline_size_v3; | ||
714 | g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq = | ||
715 | set_pmu_cmdline_args_cpufreq_v3; | ||
716 | g->ops.pmu_ver.set_pmu_cmdline_args_secure_mode = | ||
717 | set_pmu_cmdline_args_secure_mode_v3; | ||
718 | g->ops.pmu_ver.set_pmu_cmdline_args_trace_size = | ||
719 | set_pmu_cmdline_args_falctracesize_v3; | ||
720 | g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_base = | ||
721 | set_pmu_cmdline_args_falctracedmabase_v3; | ||
722 | g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_idx = | ||
723 | set_pmu_cmdline_args_falctracedmaidx_v3; | ||
724 | g->ops.pmu_ver.get_pmu_cmdline_args_ptr = | ||
725 | get_pmu_cmdline_args_ptr_v3; | ||
726 | g->ops.pmu_ver.get_pmu_allocation_struct_size = | ||
727 | get_pmu_allocation_size_v1; | ||
728 | g->ops.pmu_ver.set_pmu_allocation_ptr = | ||
729 | set_pmu_allocation_ptr_v1; | ||
730 | g->ops.pmu_ver.pmu_allocation_set_dmem_size = | ||
731 | pmu_allocation_set_dmem_size_v1; | ||
732 | g->ops.pmu_ver.pmu_allocation_get_dmem_size = | ||
733 | pmu_allocation_get_dmem_size_v1; | ||
734 | g->ops.pmu_ver.pmu_allocation_get_dmem_offset = | ||
735 | pmu_allocation_get_dmem_offset_v1; | ||
736 | g->ops.pmu_ver.pmu_allocation_get_dmem_offset_addr = | ||
737 | pmu_allocation_get_dmem_offset_addr_v1; | ||
738 | g->ops.pmu_ver.pmu_allocation_set_dmem_offset = | ||
739 | pmu_allocation_set_dmem_offset_v1; | ||
740 | g->ops.pmu_ver.get_pmu_init_msg_pmu_queue_params = | ||
741 | get_pmu_init_msg_pmu_queue_params_v1; | ||
742 | g->ops.pmu_ver.get_pmu_msg_pmu_init_msg_ptr = | ||
743 | get_pmu_msg_pmu_init_msg_ptr_v1; | ||
744 | g->ops.pmu_ver.get_pmu_init_msg_pmu_sw_mg_off = | ||
745 | get_pmu_init_msg_pmu_sw_mg_off_v1; | ||
746 | g->ops.pmu_ver.get_pmu_init_msg_pmu_sw_mg_size = | ||
747 | get_pmu_init_msg_pmu_sw_mg_size_v1; | ||
748 | g->ops.pmu_ver.get_pmu_perfmon_cmd_start_size = | ||
749 | get_pmu_perfmon_cmd_start_size_v1; | ||
750 | g->ops.pmu_ver.get_perfmon_cmd_start_offsetofvar = | ||
751 | get_perfmon_cmd_start_offsetofvar_v1; | ||
752 | g->ops.pmu_ver.perfmon_start_set_cmd_type = | ||
753 | perfmon_start_set_cmd_type_v1; | ||
754 | g->ops.pmu_ver.perfmon_start_set_group_id = | ||
755 | perfmon_start_set_group_id_v1; | ||
756 | g->ops.pmu_ver.perfmon_start_set_state_id = | ||
757 | perfmon_start_set_state_id_v1; | ||
758 | g->ops.pmu_ver.perfmon_start_set_flags = | ||
759 | perfmon_start_set_flags_v1; | ||
760 | g->ops.pmu_ver.perfmon_start_get_flags = | ||
761 | perfmon_start_get_flags_v1; | ||
762 | g->ops.pmu_ver.get_pmu_perfmon_cmd_init_size = | ||
763 | get_pmu_perfmon_cmd_init_size_v1; | ||
764 | g->ops.pmu_ver.get_perfmon_cmd_init_offsetofvar = | ||
765 | get_perfmon_cmd_init_offsetofvar_v1; | ||
766 | g->ops.pmu_ver.perfmon_cmd_init_set_sample_buffer = | ||
767 | perfmon_cmd_init_set_sample_buffer_v1; | ||
768 | g->ops.pmu_ver.perfmon_cmd_init_set_dec_cnt = | ||
769 | perfmon_cmd_init_set_dec_cnt_v1; | ||
770 | g->ops.pmu_ver.perfmon_cmd_init_set_base_cnt_id = | ||
771 | perfmon_cmd_init_set_base_cnt_id_v1; | ||
772 | g->ops.pmu_ver.perfmon_cmd_init_set_samp_period_us = | ||
773 | perfmon_cmd_init_set_samp_period_us_v1; | ||
774 | g->ops.pmu_ver.perfmon_cmd_init_set_num_cnt = | ||
775 | perfmon_cmd_init_set_num_cnt_v1; | ||
776 | g->ops.pmu_ver.perfmon_cmd_init_set_mov_avg = | ||
777 | perfmon_cmd_init_set_mov_avg_v1; | ||
778 | g->ops.pmu_ver.get_pmu_seq_in_a_ptr = | ||
779 | get_pmu_sequence_in_alloc_ptr_v1; | ||
780 | g->ops.pmu_ver.get_pmu_seq_out_a_ptr = | ||
781 | get_pmu_sequence_out_alloc_ptr_v1; | ||
782 | break; | ||
664 | case APP_VERSION_GM20B_3: | 783 | case APP_VERSION_GM20B_3: |
665 | case APP_VERSION_GM20B_2: | 784 | case APP_VERSION_GM20B_2: |
666 | g->ops.pmu_ver.get_perfmon_cntr_ptr = get_perfmon_cntr_ptr_v2; | 785 | g->ops.pmu_ver.get_perfmon_cntr_ptr = get_perfmon_cntr_ptr_v2; |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h index 823f5484..8b79af95 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | |||
@@ -49,6 +49,7 @@ | |||
49 | /* Mapping between AP_CTRLs and Idle counters */ | 49 | /* Mapping between AP_CTRLs and Idle counters */ |
50 | #define PMU_AP_IDLE_MASK_GRAPHICS (PMU_AP_IDLE_MASK_HIST_IDX_1) | 50 | #define PMU_AP_IDLE_MASK_GRAPHICS (PMU_AP_IDLE_MASK_HIST_IDX_1) |
51 | 51 | ||
52 | #define APP_VERSION_GM20B_4 19008461 | ||
52 | #define APP_VERSION_GM20B_3 18935575 | 53 | #define APP_VERSION_GM20B_3 18935575 |
53 | #define APP_VERSION_GM20B_2 18694072 | 54 | #define APP_VERSION_GM20B_2 18694072 |
54 | #define APP_VERSION_GM20B_1 18547257 | 55 | #define APP_VERSION_GM20B_1 18547257 |
@@ -349,6 +350,18 @@ struct pmu_cmdline_args_v2 { | |||
349 | struct pmu_mem_v1 gc6_ctx; /* dmem offset of gc6 context */ | 350 | struct pmu_mem_v1 gc6_ctx; /* dmem offset of gc6 context */ |
350 | }; | 351 | }; |
351 | 352 | ||
353 | struct pmu_cmdline_args_v3 { | ||
354 | u32 reserved; | ||
355 | u32 cpu_freq_hz; /* Frequency of the clock driving PMU */ | ||
356 | u32 falc_trace_size; /* falctrace buffer size (bytes) */ | ||
357 | u32 falc_trace_dma_base; /* 256-byte block address */ | ||
358 | u32 falc_trace_dma_idx; /* dmaIdx for DMA operations */ | ||
359 | u8 secure_mode; | ||
360 | u8 raise_priv_sec; /*Raise priv level required for desired | ||
361 | registers*/ | ||
362 | struct pmu_mem_v1 gc6_ctx; /* dmem offset of gc6 context */ | ||
363 | }; | ||
364 | |||
352 | #define GK20A_PMU_TRACE_BUFSIZE 0x4000 /* 4K */ | 365 | #define GK20A_PMU_TRACE_BUFSIZE 0x4000 /* 4K */ |
353 | #define GK20A_PMU_DMEM_BLKSIZE2 8 | 366 | #define GK20A_PMU_DMEM_BLKSIZE2 8 |
354 | 367 | ||
@@ -1174,6 +1187,7 @@ struct pmu_gk20a { | |||
1174 | struct pmu_cmdline_args_v0 args_v0; | 1187 | struct pmu_cmdline_args_v0 args_v0; |
1175 | struct pmu_cmdline_args_v1 args_v1; | 1188 | struct pmu_cmdline_args_v1 args_v1; |
1176 | struct pmu_cmdline_args_v2 args_v2; | 1189 | struct pmu_cmdline_args_v2 args_v2; |
1190 | struct pmu_cmdline_args_v3 args_v3; | ||
1177 | }; | 1191 | }; |
1178 | unsigned long perfmon_events_cnt; | 1192 | unsigned long perfmon_events_cnt; |
1179 | bool perfmon_sampling_enabled; | 1193 | bool perfmon_sampling_enabled; |