gpu: nvgpu: ZBC update without idle

Do ZBC updates without forcing engine idle first.

Bug 1698013

Change-Id: I99218c8cfd02be05dace2003b8d91921765f7ca9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/829145

5 files changed, 15 insertions, 78 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index e43e58a0..3542a597 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -782,6 +782,14 @@ static inline u32 gk20a_readl(struct gk20a *g, u32 r)
         gk20a_dbg(gpu_dbg_reg, " r=0x%x v=0x%x", r, v);
         return v;
 }
+static inline void gk20a_writel_check(struct gk20a *g, u32 r, u32 v)
+{
+        gk20a_dbg(gpu_dbg_reg, " r=0x%x v=0x%x", r, v);
+        wmb();
+        do {
+                writel_relaxed(v, g->regs + r);
+        } while (readl(g->regs + r) != v);
+}
 
 static inline void gk20a_bar1_writel(struct gk20a *g, u32 b, u32 v)
 {
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 0cb18665..090f95a5 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -3456,42 +3456,6 @@ int gr_gk20a_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr,
         return 0;
 }
 
-void gr_gk20a_pmu_save_zbc(struct gk20a *g, u32 entries)
-{
-        struct fifo_gk20a *f = &g->fifo;
-        struct fifo_engine_info_gk20a *gr_info =
-                f->engine_info + ENGINE_GR_GK20A;
-        unsigned long end_jiffies = jiffies +
-                msecs_to_jiffies(gk20a_get_gr_idle_timeout(g));
-        u32 ret;
-
-        ret = gk20a_fifo_disable_engine_activity(g, gr_info, true);
-        if (ret) {
-                gk20a_err(dev_from_gk20a(g),
-                        "failed to disable gr engine activity\n");
-                return;
-        }
-
-        ret = g->ops.gr.wait_empty(g, end_jiffies, GR_IDLE_CHECK_DEFAULT);
-        if (ret) {
-                gk20a_err(dev_from_gk20a(g),
-                        "failed to idle graphics\n");
-                goto clean_up;
-        }
-
-        /* update zbc */
-        gk20a_pmu_save_zbc(g, entries);
-
-clean_up:
-        ret = gk20a_fifo_enable_engine_activity(g, gr_info);
-        if (ret) {
-                gk20a_err(dev_from_gk20a(g),
-                        "failed to enable gr engine activity\n");
-        }
-
-        return;
-}
-
 int gr_gk20a_add_zbc(struct gk20a *g, struct gr_gk20a *gr,
                      struct zbc_entry *zbc_val)
 {
@@ -3584,7 +3548,7 @@ int gr_gk20a_add_zbc(struct gk20a *g, struct gr_gk20a *gr,
                 /* update zbc for elpg only when new entry is added */
                 entries = max(gr->max_used_color_index,
                                         gr->max_used_depth_index);
-                gr_gk20a_pmu_save_zbc(g, entries);
+                gk20a_pmu_save_zbc(g, entries);
         }
 
 err_mutex:
@@ -3739,47 +3703,13 @@ int gr_gk20a_load_zbc_default_table(struct gk20a *g, struct gr_gk20a *gr)
         return 0;
 }
 
-static int _gk20a_gr_zbc_set_table(struct gk20a *g, struct gr_gk20a *gr,
-                        struct zbc_entry *zbc_val)
-{
-        struct fifo_gk20a *f = &g->fifo;
-        struct fifo_engine_info_gk20a *gr_info = f->engine_info + ENGINE_GR_GK20A;
-        unsigned long end_jiffies;
-        int ret;
-
-        ret = gk20a_fifo_disable_engine_activity(g, gr_info, true);
-        if (ret) {
-                gk20a_err(dev_from_gk20a(g),
-                        "failed to disable gr engine activity\n");
-                return ret;
-        }
-
-        end_jiffies = jiffies + msecs_to_jiffies(gk20a_get_gr_idle_timeout(g));
-        ret = g->ops.gr.wait_empty(g, end_jiffies, GR_IDLE_CHECK_DEFAULT);
-        if (ret) {
-                gk20a_err(dev_from_gk20a(g),
-                        "failed to idle graphics\n");
-                goto clean_up;
-        }
-
-        ret = gr_gk20a_add_zbc(g, gr, zbc_val);
-
-clean_up:
-        if (gk20a_fifo_enable_engine_activity(g, gr_info)) {
-                gk20a_err(dev_from_gk20a(g),
-                        "failed to enable gr engine activity\n");
-        }
-
-        return ret;
-}
-
 int gk20a_gr_zbc_set_table(struct gk20a *g, struct gr_gk20a *gr,
                         struct zbc_entry *zbc_val)
 {
         gk20a_dbg_fn("");
 
         return gr_gk20a_elpg_protected_call(g,
-                _gk20a_gr_zbc_set_table(g, gr, zbc_val));
+                gr_gk20a_add_zbc(g, gr, zbc_val));
 }
 
 void gr_gk20a_init_blcg_mode(struct gk20a *g, u32 mode, u32 engine)
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
index 6444a22d..55c5ceb7 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
@@ -429,8 +429,6 @@ int gr_gk20a_fecs_set_reglist_virtual_addr(struct gk20a *g, u64 pmu_va);
 void gr_gk20a_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine);
 void gr_gk20a_init_blcg_mode(struct gk20a *g, u32 mode, u32 engine);
 
-void gr_gk20a_pmu_save_zbc(struct gk20a *g, u32 entries);
-
 /* sm */
 bool gk20a_gr_sm_debugger_attached(struct gk20a *g);
 
diff --git a/drivers/gpu/nvgpu/gk20a/ltc_common.c b/drivers/gpu/nvgpu/gk20a/ltc_common.c
index 6fbd0c2d..1c18418c 100644
--- a/drivers/gpu/nvgpu/gk20a/ltc_common.c
+++ b/drivers/gpu/nvgpu/gk20a/ltc_common.c
@@ -52,9 +52,10 @@ static void gk20a_ltc_set_zbc_color_entry(struct gk20a *g,
                      ltc_ltcs_ltss_dstg_zbc_index_address_f(real_index));
 
         for (i = 0;
-             i < ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(); i++)
-                gk20a_writel(g, ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(i),
+             i < ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(); i++) {
+                gk20a_writel_check(g, ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(i),
                              color_val->color_l2[i]);
+        }
 }
 
 /*
@@ -69,7 +70,7 @@ static void gk20a_ltc_set_zbc_depth_entry(struct gk20a *g,
         gk20a_writel(g, ltc_ltcs_ltss_dstg_zbc_index_r(),
                      ltc_ltcs_ltss_dstg_zbc_index_address_f(real_index));
 
-        gk20a_writel(g, ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(),
+        gk20a_writel_check(g, ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(),
                      depth_val->depth);
 }
 
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
index 744a852e..0ff3838a 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
@@ -2737,7 +2737,7 @@ static void pmu_setup_hw_enable_elpg(struct gk20a *g)
 
         pmu->zbc_ready = true;
         /* Save zbc table after PMU is initialized. */
-        gr_gk20a_pmu_save_zbc(g, 0xf);
+        gk20a_pmu_save_zbc(g, 0xf);
 
         if (g->elpg_enabled) {
                 /* Init reg with prod values*/