diff options
author | Thomas Fleury <tfleury@nvidia.com> | 2019-08-27 10:09:51 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2020-01-30 02:42:46 -0500 |
commit | e41fd090315ff37fa09314a8cfde6d384385e17a (patch) | |
tree | 8d96902ff2749cd94f0630202af56a577a780a01 /drivers/gpu/nvgpu/gk20a | |
parent | e0587aaf4d8f803004365eef2b08c0becd1042cb (diff) |
gpu: nvgpu: use refcnt for ch mmu_debug_mode
Replaced ch->mmu_debug_mode_enabled with ch->mmu_debug_mode_refcnt.
If channel is enabled multiple times by userspace, then ref count is
updated accordingly. There is an expectation that enable/disable
calls are balanced for setting channel's mmu debug mode.
When unbinding the channel, decrease refcnt for the channel until it
reaches 0.
Also, removed tsg parameter from nvgpu_tsg_set_mmu_debug_mode as it
can be retrieved from ch.
Bug 2515097
Bug 2713590
Change-Id: If334e374a55bd14ae219edbfd3b1fce5ff25c226
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2184702
(cherry picked from commit f422aee39387a5aa337de69cc21a67f16697ae0e)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2208772
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Kajetan Dutka <kdutka@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: Kajetan Dutka <kdutka@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 1b18a8f9..4d62d8e9 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GK20A Graphics FIFO (gr host) | 2 | * GK20A Graphics FIFO (gr host) |
3 | * | 3 | * |
4 | * Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2011-2020, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -2250,6 +2250,15 @@ int gk20a_fifo_tsg_unbind_channel(struct channel_gk20a *ch) | |||
2250 | goto fail_enable_tsg; | 2250 | goto fail_enable_tsg; |
2251 | } | 2251 | } |
2252 | 2252 | ||
2253 | while (ch->mmu_debug_mode_refcnt > 0U) { | ||
2254 | err = nvgpu_tsg_set_mmu_debug_mode(ch, false); | ||
2255 | if (err != 0) { | ||
2256 | nvgpu_err(g, "disable mmu debug mode failed ch:%u", | ||
2257 | ch->chid); | ||
2258 | break; | ||
2259 | } | ||
2260 | } | ||
2261 | |||
2253 | /* Remove channel from TSG and re-enable rest of the channels */ | 2262 | /* Remove channel from TSG and re-enable rest of the channels */ |
2254 | nvgpu_rwsem_down_write(&tsg->ch_list_lock); | 2263 | nvgpu_rwsem_down_write(&tsg->ch_list_lock); |
2255 | nvgpu_list_del(&ch->ch_entry); | 2264 | nvgpu_list_del(&ch->ch_entry); |