gpu: nvgpu: Add MC APIs for reset masks

Add API for querying reset mask corresponding to a unit. The reset
masks need to be read from MC HW header, and we do not want all
units to access Mc HW headers themselves.

JIRA NVGPU-954

Change-Id: I49ebbd891569de634bfc71afcecc8cd2358805c0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1823384
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

7 files changed, 16 insertions, 21 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c
index 436d3205..6df8f6e4 100644
--- a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c
@@ -39,7 +39,6 @@
 #include <nvgpu/hw/gk20a/hw_ccsr_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_ram_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_top_gk20a.h>
-#include <nvgpu/hw/gk20a/hw_mc_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_gr_gk20a.h>
 #include <nvgpu/barrier.h>
 
diff --git a/drivers/gpu/nvgpu/gk20a/css_gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/css_gr_gk20a.c
index 00d1b196..28a3d495 100644
--- a/drivers/gpu/nvgpu/gk20a/css_gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/css_gr_gk20a.c
@@ -34,12 +34,12 @@
 #include <nvgpu/io.h>
 #include <nvgpu/utils.h>
 #include <nvgpu/channel.h>
+#include <nvgpu/unit.h>
 
 #include "gk20a.h"
 #include "css_gr_gk20a.h"
 
 #include <nvgpu/hw/gk20a/hw_perf_gk20a.h>
-#include <nvgpu/hw/gk20a/hw_mc_gk20a.h>
 
 /* check client for pointed perfmon ownership */
 #define CONTAINS_PERFMON(cl, pm)                                \
@@ -89,7 +89,7 @@ static void css_hw_reset_streaming(struct gk20a *g)
         u32 engine_status;
 
         /* reset the perfmon */
-        g->ops.mc.reset(g, mc_enable_perfmon_enabled_f());
+        g->ops.mc.reset(g, g->ops.mc.reset_mask(g, NVGPU_UNIT_PERFMON));
 
         /* RBUFEMPTY must be set -- otherwise we'll pick up */
         /* snapshot that have been queued up from earlier   */
diff --git a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c
index ef505425..adc13c3d 100644
--- a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c
@@ -31,6 +31,7 @@
 #include <nvgpu/io.h>
 #include <nvgpu/utils.h>
 #include <nvgpu/channel.h>
+#include <nvgpu/unit.h>
 
 #include "gk20a.h"
 #include "gr_gk20a.h"
@@ -39,14 +40,13 @@
 
 #include <nvgpu/hw/gk20a/hw_gr_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_perf_gk20a.h>
-#include <nvgpu/hw/gk20a/hw_mc_gk20a.h>
 
 static void gk20a_perfbuf_reset_streaming(struct gk20a *g)
 {
         u32 engine_status;
         u32 num_unread_bytes;
 
-        g->ops.mc.reset(g, mc_enable_perfmon_enabled_f());
+        g->ops.mc.reset(g, g->ops.mc.reset_mask(g, NVGPU_UNIT_PERFMON));
 
         engine_status = gk20a_readl(g, perf_pmasys_enginestatus_r());
         WARN_ON(0u ==
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index e1702bd7..3632963a 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -44,6 +44,7 @@
 #include <nvgpu/io.h>
 #include <nvgpu/utils.h>
 #include <nvgpu/channel.h>
+#include <nvgpu/unit.h>
 
 #include "gk20a.h"
 #include "mm_gk20a.h"
@@ -53,7 +54,6 @@
 #include <nvgpu/hw/gk20a/hw_ccsr_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_ram_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_top_gk20a.h>
-#include <nvgpu/hw/gk20a/hw_mc_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_gr_gk20a.h>
 
 #define FECS_METHOD_WFI_RESTORE 0x80000
@@ -822,7 +822,7 @@ int gk20a_init_fifo_reset_enable_hw(struct gk20a *g)
         nvgpu_log_fn(g, " ");
 
         /* enable pmc pfifo */
-        g->ops.mc.reset(g, mc_enable_pfifo_enabled_f());
+        g->ops.mc.reset(g, g->ops.mc.reset_mask(g, NVGPU_UNIT_FIFO));
 
         if (g->ops.clock_gating.slcg_fifo_load_gating_prod) {
                 g->ops.clock_gating.slcg_fifo_load_gating_prod(g,
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 0250e97e..6e63c138 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -42,6 +42,7 @@
 #include <nvgpu/io.h>
 #include <nvgpu/utils.h>
 #include <nvgpu/channel.h>
+#include <nvgpu/unit.h>
 
 #include "gk20a.h"
 #include "gr_gk20a.h"
@@ -4708,9 +4709,9 @@ static int gk20a_init_gr_prepare(struct gk20a *g)
         u32 err = 0;
 
         /* reset gr engine */
-        g->ops.mc.reset(g, mc_enable_pgraph_enabled_f() |
-                        mc_enable_blg_enabled_f() |
-                        mc_enable_perfmon_enabled_f());
+        g->ops.mc.reset(g, g->ops.mc.reset_mask(g, NVGPU_UNIT_GRAPH) |
+                        g->ops.mc.reset_mask(g, NVGPU_UNIT_BLG) |
+                        g->ops.mc.reset_mask(g, NVGPU_UNIT_PERFMON));
 
         gr_gk20a_load_gating_prod(g);
 
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
index 6d5bea30..2e57d01e 100644
--- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
@@ -51,7 +51,6 @@
 #include <nvgpu/hw/gk20a/hw_gmmu_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_ram_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_pram_gk20a.h>
-#include <nvgpu/hw/gk20a/hw_mc_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_flush_gk20a.h>
 
 /*
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
index f231e088..6eecc4fa 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
@@ -34,6 +34,7 @@
 #include <nvgpu/io.h>
 #include <nvgpu/clk_arb.h>
 #include <nvgpu/utils.h>
+#include <nvgpu/unit.h>
 
 #include "gk20a.h"
 #include "gr_gk20a.h"
@@ -497,24 +498,21 @@ void gk20a_write_dmatrfbase(struct gk20a *g, u32 addr)
 
 bool gk20a_pmu_is_engine_in_reset(struct gk20a *g)
 {
-        u32 pmc_enable;
         bool status = false;
 
-        pmc_enable = gk20a_readl(g, mc_enable_r());
-        if (mc_enable_pwr_v(pmc_enable) ==
-                        mc_enable_pwr_disabled_v()) {
-                status = true;
-        }
+        status = g->ops.mc.is_enabled(g, NVGPU_UNIT_PWR);
 
         return status;
 }
 
 int gk20a_pmu_engine_reset(struct gk20a *g, bool do_reset)
 {
+        u32 reset_mask = g->ops.mc.reset_mask(g, NVGPU_UNIT_PWR);
+
         if (do_reset) {
-                g->ops.mc.enable(g, mc_enable_pwr_enabled_f());
+                g->ops.mc.enable(g, reset_mask);
         } else {
-                g->ops.mc.disable(g, mc_enable_pwr_enabled_f());
+                g->ops.mc.disable(g, reset_mask);
         }
 
         return 0;
@@ -659,8 +657,6 @@ void gk20a_pmu_dump_falcon_stats(struct nvgpu_pmu *pmu)
                         pwr_falcon_exterrstat_valid_true_v()) {
                 nvgpu_err(g, "pwr_falcon_exterraddr_r : 0x%x",
                         gk20a_readl(g, pwr_falcon_exterraddr_r()));
-                nvgpu_err(g, "pmc_enable : 0x%x",
-                        gk20a_readl(g, mc_enable_r()));
         }
 
         /* Print PMU F/W debug prints */