diff options
author | Sunny He <suhe@nvidia.com> | 2017-06-30 17:40:33 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-07-24 02:35:03 -0400 |
commit | d717c69d2b1992688589ae389380fedf0b06c720 (patch) | |
tree | 5d7596070d8ab7ca53bcd8506135d99789c9b7bb /drivers/gpu/nvgpu/gk20a | |
parent | 882a5be5a45702cd94c4eddf9d01e76fd8e039a1 (diff) |
gpu: nvgpu: Reorg css HAL initialization
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the
css sub-module of the gpu_ops struct.
Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.
Jira NVGPU-74
Change-Id: I3bf696e13d359982c964c7bc470500a30555c034
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1514205
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/css_gr_gk20a.c | 22 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/css_gr_gk20a.h | 14 |
2 files changed, 18 insertions, 18 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/css_gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/css_gr_gk20a.c index 452bcd11..8f655b26 100644 --- a/drivers/gpu/nvgpu/gk20a/css_gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/css_gr_gk20a.c | |||
@@ -72,7 +72,7 @@ static inline u32 css_hw_get_pending_snapshots(struct gk20a *g) | |||
72 | } | 72 | } |
73 | 73 | ||
74 | /* informs hw how many snapshots have been processed (frees up fifo space) */ | 74 | /* informs hw how many snapshots have been processed (frees up fifo space) */ |
75 | static inline void css_hw_set_handled_snapshots(struct gk20a *g, u32 done) | 75 | inline void css_hw_set_handled_snapshots(struct gk20a *g, u32 done) |
76 | { | 76 | { |
77 | if (done > 0) { | 77 | if (done > 0) { |
78 | gk20a_writel(g, perf_pmasys_mem_bump_r(), | 78 | gk20a_writel(g, perf_pmasys_mem_bump_r(), |
@@ -127,7 +127,7 @@ static int css_gr_create_shared_data(struct gr_gk20a *gr) | |||
127 | return 0; | 127 | return 0; |
128 | } | 128 | } |
129 | 129 | ||
130 | static int css_hw_enable_snapshot(struct channel_gk20a *ch, | 130 | int css_hw_enable_snapshot(struct channel_gk20a *ch, |
131 | struct gk20a_cs_snapshot_client *cs_client) | 131 | struct gk20a_cs_snapshot_client *cs_client) |
132 | { | 132 | { |
133 | struct gk20a *g = ch->g; | 133 | struct gk20a *g = ch->g; |
@@ -203,7 +203,7 @@ failed_allocation: | |||
203 | return ret; | 203 | return ret; |
204 | } | 204 | } |
205 | 205 | ||
206 | static void css_hw_disable_snapshot(struct gr_gk20a *gr) | 206 | void css_hw_disable_snapshot(struct gr_gk20a *gr) |
207 | { | 207 | { |
208 | struct gk20a *g = gr->g; | 208 | struct gk20a *g = gr->g; |
209 | struct gk20a_cs_snapshot *data = gr->cs_data; | 209 | struct gk20a_cs_snapshot *data = gr->cs_data; |
@@ -399,7 +399,7 @@ next_hw_fifo_entry: | |||
399 | return 0; | 399 | return 0; |
400 | } | 400 | } |
401 | 401 | ||
402 | static u32 css_gr_allocate_perfmon_ids(struct gk20a_cs_snapshot *data, | 402 | u32 css_gr_allocate_perfmon_ids(struct gk20a_cs_snapshot *data, |
403 | u32 count) | 403 | u32 count) |
404 | { | 404 | { |
405 | unsigned long *pids = data->perfmon_ids; | 405 | unsigned long *pids = data->perfmon_ids; |
@@ -415,7 +415,7 @@ static u32 css_gr_allocate_perfmon_ids(struct gk20a_cs_snapshot *data, | |||
415 | return f; | 415 | return f; |
416 | } | 416 | } |
417 | 417 | ||
418 | static u32 css_gr_release_perfmon_ids(struct gk20a_cs_snapshot *data, | 418 | u32 css_gr_release_perfmon_ids(struct gk20a_cs_snapshot *data, |
419 | u32 start, | 419 | u32 start, |
420 | u32 count) | 420 | u32 count) |
421 | { | 421 | { |
@@ -653,7 +653,7 @@ void gr_gk20a_free_cyclestats_snapshot_data(struct gk20a *g) | |||
653 | nvgpu_mutex_destroy(&gr->cs_lock); | 653 | nvgpu_mutex_destroy(&gr->cs_lock); |
654 | } | 654 | } |
655 | 655 | ||
656 | static int css_hw_check_data_available(struct channel_gk20a *ch, u32 *pending, | 656 | int css_hw_check_data_available(struct channel_gk20a *ch, u32 *pending, |
657 | bool *hw_overflow) | 657 | bool *hw_overflow) |
658 | { | 658 | { |
659 | struct gk20a *g = ch->g; | 659 | struct gk20a *g = ch->g; |
@@ -670,13 +670,3 @@ static int css_hw_check_data_available(struct channel_gk20a *ch, u32 *pending, | |||
670 | *hw_overflow = css_hw_get_overflow_status(g); | 670 | *hw_overflow = css_hw_get_overflow_status(g); |
671 | return 0; | 671 | return 0; |
672 | } | 672 | } |
673 | |||
674 | void gk20a_init_css_ops(struct gpu_ops *gops) | ||
675 | { | ||
676 | gops->css.enable_snapshot = css_hw_enable_snapshot; | ||
677 | gops->css.disable_snapshot = css_hw_disable_snapshot; | ||
678 | gops->css.check_data_available = css_hw_check_data_available; | ||
679 | gops->css.set_handled_snapshots = css_hw_set_handled_snapshots; | ||
680 | gops->css.allocate_perfmon_ids = css_gr_allocate_perfmon_ids; | ||
681 | gops->css.release_perfmon_ids = css_gr_release_perfmon_ids; | ||
682 | } | ||
diff --git a/drivers/gpu/nvgpu/gk20a/css_gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/css_gr_gk20a.h index a95eaeae..804308bc 100644 --- a/drivers/gpu/nvgpu/gk20a/css_gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/css_gr_gk20a.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GK20A Cycle stats snapshots support (subsystem for gr_gk20a). | 2 | * GK20A Cycle stats snapshots support (subsystem for gr_gk20a). |
3 | * | 3 | * |
4 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -121,6 +121,16 @@ struct gk20a_cs_snapshot { | |||
121 | struct gk20a_cs_snapshot_fifo_entry *hw_get; | 121 | struct gk20a_cs_snapshot_fifo_entry *hw_get; |
122 | }; | 122 | }; |
123 | 123 | ||
124 | void gk20a_init_css_ops(struct gpu_ops *gops); | 124 | inline void css_hw_set_handled_snapshots(struct gk20a *g, u32 done); |
125 | int css_hw_enable_snapshot(struct channel_gk20a *ch, | ||
126 | struct gk20a_cs_snapshot_client *cs_client); | ||
127 | void css_hw_disable_snapshot(struct gr_gk20a *gr); | ||
128 | u32 css_gr_allocate_perfmon_ids(struct gk20a_cs_snapshot *data, | ||
129 | u32 count); | ||
130 | u32 css_gr_release_perfmon_ids(struct gk20a_cs_snapshot *data, | ||
131 | u32 start, | ||
132 | u32 count); | ||
133 | int css_hw_check_data_available(struct channel_gk20a *ch, u32 *pending, | ||
134 | bool *hw_overflow); | ||
125 | 135 | ||
126 | #endif /* CSS_GR_GK20A_H */ | 136 | #endif /* CSS_GR_GK20A_H */ |