diff options
author | Konsta Holtta <kholtta@nvidia.com> | 2018-09-21 08:28:15 -0400 |
---|---|---|
committer | Konsta Holtta <kholtta@nvidia.com> | 2018-09-21 10:55:39 -0400 |
commit | ce5228e09411f9c54e96cfb0f7e9c857fd9b480d (patch) | |
tree | 26bbc69aa41fc1cb78746540cbf395f6a9cdda12 /drivers/gpu/nvgpu/gk20a | |
parent | 84097d54f3b9ff242c4c3fb3c0a95353e8513b33 (diff) |
Revert "gpu: nvgpu: refactor SET_SM_EXCEPTION_MASK ioctl"
This reverts commit c5810a670d367ae1dc405fcc3108e11265df34bb.
Bug 2400508
Jira VQRM-4806
Bug 200447406
Bug 2331747
Change-Id: Ie2a2c21f9285ff0349c7033fae24766a7117b462
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1837223
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/tsg_gk20a.c | 24 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/tsg_gk20a.h | 3 |
2 files changed, 0 insertions, 27 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c index 43ee8d7c..885ce172 100644 --- a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c | |||
@@ -367,7 +367,6 @@ void gk20a_tsg_release(struct nvgpu_ref *ref) | |||
367 | if(tsg->sm_error_states != NULL) { | 367 | if(tsg->sm_error_states != NULL) { |
368 | nvgpu_kfree(g, tsg->sm_error_states); | 368 | nvgpu_kfree(g, tsg->sm_error_states); |
369 | tsg->sm_error_states = NULL; | 369 | tsg->sm_error_states = NULL; |
370 | nvgpu_mutex_destroy(&tsg->sm_exception_mask_lock); | ||
371 | } | 370 | } |
372 | 371 | ||
373 | /* unhook all events created on this TSG */ | 372 | /* unhook all events created on this TSG */ |
@@ -408,11 +407,6 @@ int gk20a_tsg_alloc_sm_error_states_mem(struct gk20a *g, | |||
408 | int err = 0; | 407 | int err = 0; |
409 | 408 | ||
410 | if (tsg->sm_error_states != NULL) { | 409 | if (tsg->sm_error_states != NULL) { |
411 | return -EINVAL; | ||
412 | } | ||
413 | |||
414 | err = nvgpu_mutex_init(&tsg->sm_exception_mask_lock); | ||
415 | if (err) { | ||
416 | return err; | 410 | return err; |
417 | } | 411 | } |
418 | 412 | ||
@@ -421,7 +415,6 @@ int gk20a_tsg_alloc_sm_error_states_mem(struct gk20a *g, | |||
421 | * num_sm); | 415 | * num_sm); |
422 | if (tsg->sm_error_states == NULL) { | 416 | if (tsg->sm_error_states == NULL) { |
423 | nvgpu_err(g, "sm_error_states mem allocation failed"); | 417 | nvgpu_err(g, "sm_error_states mem allocation failed"); |
424 | nvgpu_mutex_destroy(&tsg->sm_exception_mask_lock); | ||
425 | err = -ENOMEM; | 418 | err = -ENOMEM; |
426 | } | 419 | } |
427 | 420 | ||
@@ -447,20 +440,3 @@ void gk20a_tsg_update_sm_error_state_locked(struct tsg_gk20a *tsg, | |||
447 | tsg_sm_error_states->hww_warp_esr_report_mask = | 440 | tsg_sm_error_states->hww_warp_esr_report_mask = |
448 | sm_error_state->hww_warp_esr_report_mask; | 441 | sm_error_state->hww_warp_esr_report_mask; |
449 | } | 442 | } |
450 | |||
451 | int gk20a_tsg_set_sm_exception_type_mask(struct channel_gk20a *ch, | ||
452 | u32 exception_mask) | ||
453 | { | ||
454 | struct tsg_gk20a *tsg; | ||
455 | |||
456 | tsg = tsg_gk20a_from_ch(ch); | ||
457 | if (!tsg) { | ||
458 | return -EINVAL; | ||
459 | } | ||
460 | |||
461 | nvgpu_mutex_acquire(&tsg->sm_exception_mask_lock); | ||
462 | tsg->sm_exception_mask_type = exception_mask; | ||
463 | nvgpu_mutex_release(&tsg->sm_exception_mask_lock); | ||
464 | |||
465 | return 0; | ||
466 | } | ||
diff --git a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h index d13cd388..1e3be553 100644 --- a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h | |||
@@ -82,7 +82,6 @@ struct tsg_gk20a { | |||
82 | #define NVGPU_SM_EXCEPTION_TYPE_MASK_NONE (0x0U) | 82 | #define NVGPU_SM_EXCEPTION_TYPE_MASK_NONE (0x0U) |
83 | #define NVGPU_SM_EXCEPTION_TYPE_MASK_FATAL (0x1U << 0) | 83 | #define NVGPU_SM_EXCEPTION_TYPE_MASK_FATAL (0x1U << 0) |
84 | u32 sm_exception_mask_type; | 84 | u32 sm_exception_mask_type; |
85 | struct nvgpu_mutex sm_exception_mask_lock; | ||
86 | }; | 85 | }; |
87 | 86 | ||
88 | int gk20a_enable_tsg(struct tsg_gk20a *tsg); | 87 | int gk20a_enable_tsg(struct tsg_gk20a *tsg); |
@@ -104,8 +103,6 @@ int gk20a_tsg_alloc_sm_error_states_mem(struct gk20a *g, | |||
104 | void gk20a_tsg_update_sm_error_state_locked(struct tsg_gk20a *tsg, | 103 | void gk20a_tsg_update_sm_error_state_locked(struct tsg_gk20a *tsg, |
105 | u32 sm_id, | 104 | u32 sm_id, |
106 | struct nvgpu_tsg_sm_error_state *sm_error_state); | 105 | struct nvgpu_tsg_sm_error_state *sm_error_state); |
107 | int gk20a_tsg_set_sm_exception_type_mask(struct channel_gk20a *ch, | ||
108 | u32 exception_mask); | ||
109 | 106 | ||
110 | struct gk20a_event_id_data { | 107 | struct gk20a_event_id_data { |
111 | struct gk20a *g; | 108 | struct gk20a *g; |