diff options
author | Sam Payne <spayne@nvidia.com> | 2015-01-26 17:02:25 -0500 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-04-04 21:08:17 -0400 |
commit | ce3afaaaf6092f46b2db0f8835e4d4b9b46ef1a4 (patch) | |
tree | bd06822411f5601c5ea5c7a9059c1d2c7710c64e /drivers/gpu/nvgpu/gk20a | |
parent | f3a920cb01d1517db5432c8062b660d6b60eb4de (diff) |
gpu: nvgpu: disable ce2 interrupts when unhandled
ce2 interrupts enabled only on gk20a and gm20b when
interrupts are handled through hal
Change-Id: Ib570db8f5f41e71e768b95e781153ec8a5d20015
Signed-off-by: Sam Payne <spayne@nvidia.com>
Reviewed-on: http://git-master/r/677447
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/ce2_gk20a.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/ce2_gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/hal_gk20a.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/mc_gk20a.c | 10 |
6 files changed, 21 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c index 75df4ce5..ce23c59a 100644 --- a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c | |||
@@ -92,4 +92,8 @@ void gk20a_ce2_nonstall_isr(struct gk20a *g) | |||
92 | 92 | ||
93 | return; | 93 | return; |
94 | } | 94 | } |
95 | 95 | void gk20a_init_ce2(struct gpu_ops *gops) | |
96 | { | ||
97 | gops->ce2.isr_stall = gk20a_ce2_isr; | ||
98 | gops->ce2.isr_nonstall = gk20a_ce2_nonstall_isr; | ||
99 | } | ||
diff --git a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h index 0a9ec62a..bf4e3066 100644 --- a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h | |||
@@ -24,6 +24,7 @@ | |||
24 | #include "channel_gk20a.h" | 24 | #include "channel_gk20a.h" |
25 | #include "tsg_gk20a.h" | 25 | #include "tsg_gk20a.h" |
26 | 26 | ||
27 | void gk20a_init_ce2(struct gpu_ops *gops); | ||
27 | void gk20a_ce2_isr(struct gk20a *g); | 28 | void gk20a_ce2_isr(struct gk20a *g); |
28 | void gk20a_ce2_nonstall_isr(struct gk20a *g); | 29 | void gk20a_ce2_nonstall_isr(struct gk20a *g); |
29 | 30 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index b9183e76..cf1242ab 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -145,6 +145,9 @@ u32 gk20a_fifo_engine_interrupt_mask(struct gk20a *g) | |||
145 | 145 | ||
146 | for (i = 0; i < g->fifo.max_engines; i++) { | 146 | for (i = 0; i < g->fifo.max_engines; i++) { |
147 | u32 intr_id = g->fifo.engine_info[i].intr_id; | 147 | u32 intr_id = g->fifo.engine_info[i].intr_id; |
148 | if (i == ENGINE_CE2_GK20A && | ||
149 | (!g->ops.ce2.isr_stall || !g->ops.ce2.isr_nonstall)) | ||
150 | continue; | ||
148 | 151 | ||
149 | if (intr_id) | 152 | if (intr_id) |
150 | eng_intr_mask |= BIT(intr_id); | 153 | eng_intr_mask |= BIT(intr_id); |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index ef8068e5..1157390a 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -88,6 +88,10 @@ struct gpu_ops { | |||
88 | void (*flush)(struct gk20a *g); | 88 | void (*flush)(struct gk20a *g); |
89 | } ltc; | 89 | } ltc; |
90 | struct { | 90 | struct { |
91 | void (*isr_stall)(struct gk20a *g); | ||
92 | void (*isr_nonstall)(struct gk20a *g); | ||
93 | } ce2; | ||
94 | struct { | ||
91 | int (*init_fs_state)(struct gk20a *g); | 95 | int (*init_fs_state)(struct gk20a *g); |
92 | void (*access_smpc_reg)(struct gk20a *g, u32 quad, u32 offset); | 96 | void (*access_smpc_reg)(struct gk20a *g, u32 quad, u32 offset); |
93 | void (*bundle_cb_defaults)(struct gk20a *g); | 97 | void (*bundle_cb_defaults)(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gk20a/hal_gk20a.c b/drivers/gpu/nvgpu/gk20a/hal_gk20a.c index 0e97d551..5a9c38ea 100644 --- a/drivers/gpu/nvgpu/gk20a/hal_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/hal_gk20a.c | |||
@@ -42,7 +42,7 @@ static struct gpu_ops gk20a_ops = { | |||
42 | gr_gk20a_pg_gr_load_gating_prod, | 42 | gr_gk20a_pg_gr_load_gating_prod, |
43 | .slcg_therm_load_gating_prod = | 43 | .slcg_therm_load_gating_prod = |
44 | gr_gk20a_slcg_therm_load_gating_prod, | 44 | gr_gk20a_slcg_therm_load_gating_prod, |
45 | } | 45 | }, |
46 | }; | 46 | }; |
47 | 47 | ||
48 | int gk20a_init_hal(struct gk20a *g) | 48 | int gk20a_init_hal(struct gk20a *g) |
@@ -57,6 +57,7 @@ int gk20a_init_hal(struct gk20a *g) | |||
57 | gk20a_init_gr_ops(gops); | 57 | gk20a_init_gr_ops(gops); |
58 | gk20a_init_fb(gops); | 58 | gk20a_init_fb(gops); |
59 | gk20a_init_fifo(gops); | 59 | gk20a_init_fifo(gops); |
60 | gk20a_init_ce2(gops); | ||
60 | gk20a_init_gr_ctx(gops); | 61 | gk20a_init_gr_ctx(gops); |
61 | gk20a_init_mm(gops); | 62 | gk20a_init_mm(gops); |
62 | gk20a_init_pmu_ops(gops); | 63 | gk20a_init_pmu_ops(gops); |
diff --git a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c index 86fea3a1..4aca3424 100644 --- a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c | |||
@@ -80,8 +80,9 @@ irqreturn_t mc_gk20a_intr_thread_stall(struct gk20a *g) | |||
80 | 80 | ||
81 | if (mc_intr_0 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id)) | 81 | if (mc_intr_0 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id)) |
82 | gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g)); | 82 | gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g)); |
83 | if (mc_intr_0 & BIT(g->fifo.engine_info[ENGINE_CE2_GK20A].intr_id)) | 83 | if (mc_intr_0 & BIT(g->fifo.engine_info[ENGINE_CE2_GK20A].intr_id) |
84 | gk20a_ce2_isr(g); | 84 | && g->ops.ce2.isr_stall) |
85 | g->ops.ce2.isr_stall(g); | ||
85 | if (mc_intr_0 & mc_intr_0_pfifo_pending_f()) | 86 | if (mc_intr_0 & mc_intr_0_pfifo_pending_f()) |
86 | gk20a_fifo_isr(g); | 87 | gk20a_fifo_isr(g); |
87 | if (mc_intr_0 & mc_intr_0_pmu_pending_f()) | 88 | if (mc_intr_0 & mc_intr_0_pmu_pending_f()) |
@@ -118,8 +119,9 @@ irqreturn_t mc_gk20a_intr_thread_nonstall(struct gk20a *g) | |||
118 | gk20a_fifo_nonstall_isr(g); | 119 | gk20a_fifo_nonstall_isr(g); |
119 | if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id)) | 120 | if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id)) |
120 | gk20a_gr_nonstall_isr(g); | 121 | gk20a_gr_nonstall_isr(g); |
121 | if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_CE2_GK20A].intr_id)) | 122 | if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_CE2_GK20A].intr_id) |
122 | gk20a_ce2_nonstall_isr(g); | 123 | && g->ops.ce2.isr_nonstall) |
124 | g->ops.ce2.isr_nonstall(g); | ||
123 | 125 | ||
124 | gk20a_writel(g, mc_intr_en_1_r(), | 126 | gk20a_writel(g, mc_intr_en_1_r(), |
125 | mc_intr_en_1_inta_hardware_f()); | 127 | mc_intr_en_1_inta_hardware_f()); |