gpu: nvgpu: Add Fuse prints on PMU Halt

-Print fuse values in case of PMU halt error
-and mailbox reads 0xDEADDEAD

Bug 1737044

Change-Id: I59f5fcf4a69bdd2a2eea81a69dd99bb9c4c21e1d
Signed-off-by: Supriya <ssharatkumar@nvidia.com>
Reviewed-on: http://git-master/r/1113464
(cherry picked from commit d0320eed72c5070c4fcc7564c02fa38599984751)
Reviewed-on: http://git-master/r/1120429
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

3 files changed, 12 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index ee78c6e2..273eeaf4 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -456,6 +456,7 @@ struct gpu_ops {
                         u8 grfeaturemask);
                 int (*send_lrf_tex_ltc_dram_overide_en_dis_cmd)
                         (struct gk20a *g, u32 mask);
+                void (*dump_secure_fuses)(struct gk20a *g);
                 u32  lspmuwprinitdone;
                 u32  lsfloadedfalconid;
                 bool fecsbootstrapdone;
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
index 60c87979..4edfe90c 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
@@ -2772,6 +2772,7 @@ void gk20a_init_pmu_ops(struct gpu_ops *gops)
         gops->pmu.pmu_elpg_statistics = gk20a_pmu_elpg_statistics;
         gops->pmu.pmu_pg_grinit_param = NULL;
         gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = NULL;
+        gops->pmu.dump_secure_fuses = NULL;
 }
 
 int gk20a_init_pmu_support(struct gk20a *g)
@@ -3730,6 +3731,11 @@ void gk20a_pmu_isr(struct gk20a *g)
                 gk20a_err(dev_from_gk20a(g),
                         "pmu halt intr not implemented");
                 pmu_dump_falcon_stats(pmu);
+                if (gk20a_readl(g, pwr_pmu_mailbox_r
+                                (PMU_MODE_MISMATCH_STATUS_MAILBOX_R)) ==
+                                PMU_MODE_MISMATCH_STATUS_VAL)
+                        if (g->ops.pmu.dump_secure_fuses)
+                                g->ops.pmu.dump_secure_fuses(g);
         }
         if (intr & pwr_falcon_irqstat_exterr_true_f()) {
                 gk20a_err(dev_from_gk20a(g),
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
index 54d01947..c533ba8d 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
@@ -60,6 +60,11 @@
 #define APP_VERSION_1 17997577
 #define APP_VERSION_0 16856675
 
+/*Fuse defines*/
+#define FUSE_GCPLEX_CONFIG_FUSE_0           0x2C8
+#define PMU_MODE_MISMATCH_STATUS_MAILBOX_R  6
+#define PMU_MODE_MISMATCH_STATUS_VAL        0xDEADDEAD
+
 
 enum pmu_perfmon_cmd_start_fields {
         COUNTER_ALLOC