gpu: nvgpu: Abstract IO aperture accessors

Add abstraction of IO aperture accessors. Add new functions
gk20a_io_exists() and gk20a_io_valid_reg() to remove dependencies to
aperture fields from common code.

Implement Linux version of the abstraction by moving gk20a_readl()
and gk20a_writel() to new Linux specific io.c. Move the fields
defining IO aperture to nvgpu_os_linux.

Add t19x specific IO aperture initialization functions and add t19x
specific section to nvgpu_os_linux.

JIRA NVGPU-259

Change-Id: I09e79cda60d11a20d1099a9aaa6d2375236e94ce
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1569698
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

3 files changed, 2 insertions, 108 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c
index cac62db7..a4becda0 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.c
@@ -65,32 +65,6 @@ void __nvgpu_check_gpu_state(struct gk20a *g)
         }
 }
 
-/*
- * Locks out the driver from accessing GPU registers. This prevents access to
- * thse registers after the GPU has been clock or power gated. This should help
- * find annoying bugs where register reads and writes are silently dropped
- * after the GPU has been turned off. On older chips these reads and writes can
- * also lock the entire CPU up.
- */
-int gk20a_lockout_registers(struct gk20a *g)
-{
-        g->regs = NULL;
-        g->bar1 = NULL;
-
-        return 0;
-}
-
-/*
- * Undoes gk20a_lockout_registers().
- */
-int gk20a_restore_registers(struct gk20a *g)
-{
-        g->regs = g->regs_saved;
-        g->bar1 = g->bar1_saved;
-
-        return 0;
-}
-
 void __gk20a_warn_on_no_regs(void)
 {
         WARN_ONCE(1, "Attempted access to GPU regs after unmapping!");
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index a45a7b4e..bf10055a 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -44,6 +44,7 @@ struct nvgpu_mem_sgt;
 
 #include <nvgpu/lock.h>
 #include <nvgpu/thread.h>
+#include <nvgpu/io.h>
 #ifdef CONFIG_DEBUG_FS
 #include <linux/debugfs.h>
 #endif
@@ -1067,14 +1068,6 @@ struct gk20a {
 
         struct nvgpu_ref refcount;
 
-        struct resource *reg_mem;
-        void __iomem *regs;
-        void __iomem *regs_saved;
-
-        struct resource *bar1_mem;
-        void __iomem *bar1;
-        void __iomem *bar1_saved;
-
         const char *name;
 
         bool gpu_reset_done;
@@ -1339,81 +1332,9 @@ enum gk20a_nonstall_ops {
 };
 
 /* register accessors */
-int gk20a_lockout_registers(struct gk20a *g);
-int gk20a_restore_registers(struct gk20a *g);
-
 void __nvgpu_check_gpu_state(struct gk20a *g);
 void __gk20a_warn_on_no_regs(void);
 
-static inline void gk20a_writel(struct gk20a *g, u32 r, u32 v)
-{
-        if (unlikely(!g->regs)) {
-                __gk20a_warn_on_no_regs();
-                gk20a_dbg(gpu_dbg_reg, "r=0x%x v=0x%x (failed)", r, v);
-        } else {
-                writel_relaxed(v, g->regs + r);
-                nvgpu_smp_wmb();
-                gk20a_dbg(gpu_dbg_reg, "r=0x%x v=0x%x", r, v);
-        }
-}
-static inline u32 gk20a_readl(struct gk20a *g, u32 r)
-{
-
-        u32 v = 0xffffffff;
-
-        if (unlikely(!g->regs)) {
-                __gk20a_warn_on_no_regs();
-                gk20a_dbg(gpu_dbg_reg, "r=0x%x v=0x%x (failed)", r, v);
-        } else {
-                v = readl(g->regs + r);
-                if (v == 0xffffffff)
-                        __nvgpu_check_gpu_state(g);
-                gk20a_dbg(gpu_dbg_reg, "r=0x%x v=0x%x", r, v);
-        }
-
-        return v;
-}
-static inline void gk20a_writel_check(struct gk20a *g, u32 r, u32 v)
-{
-        if (unlikely(!g->regs)) {
-                __gk20a_warn_on_no_regs();
-                gk20a_dbg(gpu_dbg_reg, "r=0x%x v=0x%x (failed)", r, v);
-        } else {
-                nvgpu_smp_wmb();
-                do {
-                        writel_relaxed(v, g->regs + r);
-                } while (readl(g->regs + r) != v);
-                gk20a_dbg(gpu_dbg_reg, "r=0x%x v=0x%x", r, v);
-        }
-}
-
-static inline void gk20a_bar1_writel(struct gk20a *g, u32 b, u32 v)
-{
-        if (unlikely(!g->bar1)) {
-                __gk20a_warn_on_no_regs();
-                gk20a_dbg(gpu_dbg_reg, "b=0x%x v=0x%x (failed)", b, v);
-        } else {
-                nvgpu_smp_wmb();
-                writel_relaxed(v, g->bar1 + b);
-                gk20a_dbg(gpu_dbg_reg, "b=0x%x v=0x%x", b, v);
-        }
-}
-
-static inline u32 gk20a_bar1_readl(struct gk20a *g, u32 b)
-{
-        u32 v = 0xffffffff;
-
-        if (unlikely(!g->bar1)) {
-                __gk20a_warn_on_no_regs();
-                gk20a_dbg(gpu_dbg_reg, "b=0x%x v=0x%x (failed)", b, v);
-        } else {
-                v = readl(g->bar1 + b);
-                gk20a_dbg(gpu_dbg_reg, "b=0x%x v=0x%x", b, v);
-        }
-
-        return v;
-}
-
 /* convenience */
 static inline struct gk20a *gk20a_from_as(struct gk20a_as *as)
 {
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 707bfb87..6f829282 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -5256,8 +5256,7 @@ static inline bool is_valid_cyclestats_bar0_offset_gk20a(struct gk20a *g,
                 is_bar0_global_offset_whitelisted_gk20a(g, offset);
         /* resource size check in case there was a problem
          * with allocating the assumed size of bar0 */
-        valid = valid &&
-                offset < resource_size(g->regs);
+        valid = valid && gk20a_io_valid_reg(g, offset);
         return valid;
 }
 #endif