diff options
author | Scott Long <scottl@nvidia.com> | 2018-08-23 13:55:04 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-08-30 23:11:22 -0400 |
commit | bc6625b9b2a2e5ef05cedf0888c28819d3c3f412 (patch) | |
tree | ab2dad9f15885ff4b3ae698ea457d4b6d6eed4fc /drivers/gpu/nvgpu/gk20a | |
parent | cded55940e6a8d616ef9cc62cacb537a7a2ef55a (diff) |
gpu: nvgpu: fix zbc MISRA 10.1 violations
The gr_gk20a_add_zbc() routine returns a signed error
(errno) status value.
Current callers of this function use a bitwise OR to collect
the returned error status values to generate a single value
to return.
Bitwise OR on signed status values is flagged as a
violation of MISRA Rule 10.1 (not to mention that in this
case it potentially results in a garbage return value).
To eliminate such violations this change modifies the
following routines to fail immediately on the first error
from a call to gr_gk20a_add_zbc():
* gr_gk20a_load_zbc_default_table()
* gr_gv11b_load_stencil_default_tbl()
JIRA NVGPU-650
Change-Id: If733c1bb0e05943ff5d0355de729133c89233583
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1805501
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 50 |
1 files changed, 31 insertions, 19 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index d4c461af..dbf9ff05 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -3985,7 +3985,8 @@ static int gr_gk20a_load_zbc_table(struct gk20a *g, struct gr_gk20a *gr) | |||
3985 | int gr_gk20a_load_zbc_default_table(struct gk20a *g, struct gr_gk20a *gr) | 3985 | int gr_gk20a_load_zbc_default_table(struct gk20a *g, struct gr_gk20a *gr) |
3986 | { | 3986 | { |
3987 | struct zbc_entry zbc_val; | 3987 | struct zbc_entry zbc_val; |
3988 | u32 i, err; | 3988 | u32 i; |
3989 | int err; | ||
3989 | 3990 | ||
3990 | nvgpu_mutex_init(&gr->zbc_lock); | 3991 | nvgpu_mutex_init(&gr->zbc_lock); |
3991 | 3992 | ||
@@ -4001,6 +4002,9 @@ int gr_gk20a_load_zbc_default_table(struct gk20a *g, struct gr_gk20a *gr) | |||
4001 | zbc_val.color_l2[0] = 0xff000000; | 4002 | zbc_val.color_l2[0] = 0xff000000; |
4002 | zbc_val.color_ds[3] = 0x3f800000; | 4003 | zbc_val.color_ds[3] = 0x3f800000; |
4003 | err = gr_gk20a_add_zbc(g, gr, &zbc_val); | 4004 | err = gr_gk20a_add_zbc(g, gr, &zbc_val); |
4005 | if (err != 0) { | ||
4006 | goto color_fail; | ||
4007 | } | ||
4004 | 4008 | ||
4005 | /* Transparent black = (fmt 1 = zero) */ | 4009 | /* Transparent black = (fmt 1 = zero) */ |
4006 | zbc_val.format = gr_ds_zbc_color_fmt_val_zero_v(); | 4010 | zbc_val.format = gr_ds_zbc_color_fmt_val_zero_v(); |
@@ -4008,7 +4012,10 @@ int gr_gk20a_load_zbc_default_table(struct gk20a *g, struct gr_gk20a *gr) | |||
4008 | zbc_val.color_ds[i] = 0; | 4012 | zbc_val.color_ds[i] = 0; |
4009 | zbc_val.color_l2[i] = 0; | 4013 | zbc_val.color_l2[i] = 0; |
4010 | } | 4014 | } |
4011 | err |= gr_gk20a_add_zbc(g, gr, &zbc_val); | 4015 | err = gr_gk20a_add_zbc(g, gr, &zbc_val); |
4016 | if (err != 0) { | ||
4017 | goto color_fail; | ||
4018 | } | ||
4012 | 4019 | ||
4013 | /* Opaque white (i.e. solid white) = (fmt 2 = uniform 1) */ | 4020 | /* Opaque white (i.e. solid white) = (fmt 2 = uniform 1) */ |
4014 | zbc_val.format = gr_ds_zbc_color_fmt_val_unorm_one_v(); | 4021 | zbc_val.format = gr_ds_zbc_color_fmt_val_unorm_one_v(); |
@@ -4016,42 +4023,47 @@ int gr_gk20a_load_zbc_default_table(struct gk20a *g, struct gr_gk20a *gr) | |||
4016 | zbc_val.color_ds[i] = 0x3f800000; | 4023 | zbc_val.color_ds[i] = 0x3f800000; |
4017 | zbc_val.color_l2[i] = 0xffffffff; | 4024 | zbc_val.color_l2[i] = 0xffffffff; |
4018 | } | 4025 | } |
4019 | err |= gr_gk20a_add_zbc(g, gr, &zbc_val); | 4026 | err = gr_gk20a_add_zbc(g, gr, &zbc_val); |
4020 | 4027 | if (err != 0) { | |
4021 | if (!err) | 4028 | goto color_fail; |
4022 | gr->max_default_color_index = 3; | ||
4023 | else { | ||
4024 | nvgpu_err(g, | ||
4025 | "fail to load default zbc color table"); | ||
4026 | return err; | ||
4027 | } | 4029 | } |
4028 | 4030 | ||
4031 | gr->max_default_color_index = 3; | ||
4032 | |||
4029 | /* load default depth table */ | 4033 | /* load default depth table */ |
4030 | zbc_val.type = GK20A_ZBC_TYPE_DEPTH; | 4034 | zbc_val.type = GK20A_ZBC_TYPE_DEPTH; |
4031 | 4035 | ||
4032 | zbc_val.format = gr_ds_zbc_z_fmt_val_fp32_v(); | 4036 | zbc_val.format = gr_ds_zbc_z_fmt_val_fp32_v(); |
4033 | zbc_val.depth = 0x3f800000; | 4037 | zbc_val.depth = 0x3f800000; |
4034 | err = gr_gk20a_add_zbc(g, gr, &zbc_val); | 4038 | err = gr_gk20a_add_zbc(g, gr, &zbc_val); |
4039 | if (err != 0) { | ||
4040 | goto depth_fail; | ||
4041 | } | ||
4035 | 4042 | ||
4036 | zbc_val.format = gr_ds_zbc_z_fmt_val_fp32_v(); | 4043 | zbc_val.format = gr_ds_zbc_z_fmt_val_fp32_v(); |
4037 | zbc_val.depth = 0; | 4044 | zbc_val.depth = 0; |
4038 | err |= gr_gk20a_add_zbc(g, gr, &zbc_val); | 4045 | err = gr_gk20a_add_zbc(g, gr, &zbc_val); |
4039 | 4046 | if (err != 0) { | |
4040 | if (!err) | 4047 | goto depth_fail; |
4041 | gr->max_default_depth_index = 2; | ||
4042 | else { | ||
4043 | nvgpu_err(g, | ||
4044 | "fail to load default zbc depth table"); | ||
4045 | return err; | ||
4046 | } | 4048 | } |
4047 | 4049 | ||
4050 | gr->max_default_depth_index = 2; | ||
4051 | |||
4048 | if (g->ops.gr.load_zbc_s_default_tbl) { | 4052 | if (g->ops.gr.load_zbc_s_default_tbl) { |
4049 | err = g->ops.gr.load_zbc_s_default_tbl(g, gr); | 4053 | err = g->ops.gr.load_zbc_s_default_tbl(g, gr); |
4050 | if (err) | 4054 | if (err != 0) { |
4051 | return err; | 4055 | return err; |
4056 | } | ||
4052 | } | 4057 | } |
4053 | 4058 | ||
4054 | return 0; | 4059 | return 0; |
4060 | |||
4061 | color_fail: | ||
4062 | nvgpu_err(g, "fail to load default zbc color table"); | ||
4063 | return err; | ||
4064 | depth_fail: | ||
4065 | nvgpu_err(g, "fail to load default zbc depth table"); | ||
4066 | return err; | ||
4055 | } | 4067 | } |
4056 | 4068 | ||
4057 | int _gk20a_gr_zbc_set_table(struct gk20a *g, struct gr_gk20a *gr, | 4069 | int _gk20a_gr_zbc_set_table(struct gk20a *g, struct gr_gk20a *gr, |