diff options
author | Kevin Huang <kevinh@nvidia.com> | 2014-03-26 14:49:04 -0400 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-03-18 15:08:54 -0400 |
commit | b5acc421ee159c932e9e95adaa6d89a0c2141b38 (patch) | |
tree | 62ddee386d8da27e1e8f7519d739862137277a9d /drivers/gpu/nvgpu/gk20a | |
parent | a9785995d5f22aaeb659285f8aeb64d8b56982e0 (diff) |
video: tegra: host: flexible to select fw per chip
Decouple the firmware selection of different gpu architecture.
Change-Id: I62bf6b3bc51a8606c5973e475988cd5987a65a1a
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/389793
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c | 41 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.h | 7 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/hal_gk20a.c | 2 |
4 files changed, 39 insertions, 15 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index a9081a9d..c19b2bf8 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -191,6 +191,10 @@ struct gpu_ops { | |||
191 | void *(*get_pmu_seq_out_a_ptr)( | 191 | void *(*get_pmu_seq_out_a_ptr)( |
192 | struct pmu_sequence *seq); | 192 | struct pmu_sequence *seq); |
193 | } pmu_ver; | 193 | } pmu_ver; |
194 | struct { | ||
195 | int (*get_netlist_name)(int index, char *name); | ||
196 | bool (*is_fw_defined)(void); | ||
197 | } gr_ctx; | ||
194 | }; | 198 | }; |
195 | 199 | ||
196 | struct gk20a { | 200 | struct gk20a { |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c index 59404f1d..478bc073 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c | |||
@@ -96,6 +96,15 @@ static int gr_gk20a_get_netlist_name(int index, char *name) | |||
96 | return -1; | 96 | return -1; |
97 | } | 97 | } |
98 | 98 | ||
99 | bool gr_gk20a_is_firmware_defined(void) | ||
100 | { | ||
101 | #ifdef GK20A_NETLIST_IMAGE_FW_NAME | ||
102 | return true; | ||
103 | #else | ||
104 | return false; | ||
105 | #endif | ||
106 | } | ||
107 | |||
99 | static int gr_gk20a_init_ctx_vars_fw(struct gk20a *g, struct gr_gk20a *gr) | 108 | static int gr_gk20a_init_ctx_vars_fw(struct gk20a *g, struct gr_gk20a *gr) |
100 | { | 109 | { |
101 | struct device *d = dev_from_gk20a(g); | 110 | struct device *d = dev_from_gk20a(g); |
@@ -107,21 +116,21 @@ static int gr_gk20a_init_ctx_vars_fw(struct gk20a *g, struct gr_gk20a *gr) | |||
107 | 116 | ||
108 | gk20a_dbg_fn(""); | 117 | gk20a_dbg_fn(""); |
109 | 118 | ||
110 | #ifdef GK20A_NETLIST_IMAGE_FW_NAME | 119 | if (g->ops.gr_ctx.is_fw_defined()) { |
111 | net = NETLIST_FINAL; | 120 | net = NETLIST_FINAL; |
112 | max = 0; | 121 | max = 0; |
113 | major_v_hw = ~0; | 122 | major_v_hw = ~0; |
114 | g->gr.ctx_vars.dynamic = false; | 123 | g->gr.ctx_vars.dynamic = false; |
115 | #else | 124 | } else { |
116 | net = NETLIST_SLOT_A; | 125 | net = NETLIST_SLOT_A; |
117 | max = MAX_NETLIST; | 126 | max = MAX_NETLIST; |
118 | major_v_hw = gk20a_readl(g, gr_fecs_ctx_state_store_major_rev_id_r()); | 127 | major_v_hw = gk20a_readl(g, |
119 | g->gr.ctx_vars.dynamic = true; | 128 | gr_fecs_ctx_state_store_major_rev_id_r()); |
120 | #endif | 129 | g->gr.ctx_vars.dynamic = true; |
130 | } | ||
121 | 131 | ||
122 | for (; net < max; net++) { | 132 | for (; net < max; net++) { |
123 | 133 | if (g->ops.gr_ctx.get_netlist_name(net, name) != 0) { | |
124 | if (gr_gk20a_get_netlist_name(net, name) != 0) { | ||
125 | gk20a_warn(d, "invalid netlist index %d", net); | 134 | gk20a_warn(d, "invalid netlist index %d", net); |
126 | continue; | 135 | continue; |
127 | } | 136 | } |
@@ -331,3 +340,9 @@ int gr_gk20a_init_ctx_vars(struct gk20a *g, struct gr_gk20a *gr) | |||
331 | else | 340 | else |
332 | return gr_gk20a_init_ctx_vars_fw(g, gr); | 341 | return gr_gk20a_init_ctx_vars_fw(g, gr); |
333 | } | 342 | } |
343 | |||
344 | void gk20a_init_gr_ctx(struct gpu_ops *gops) | ||
345 | { | ||
346 | gops->gr_ctx.get_netlist_name = gr_gk20a_get_netlist_name; | ||
347 | gops->gr_ctx.is_fw_defined = gr_gk20a_is_firmware_defined; | ||
348 | } | ||
diff --git a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.h index 909a166a..6844ee69 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GK20A Graphics Context | 2 | * GK20A Graphics Context |
3 | * | 3 | * |
4 | * Copyright (c) 2011-2013, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -18,10 +18,10 @@ | |||
18 | #ifndef __GR_CTX_GK20A_H__ | 18 | #ifndef __GR_CTX_GK20A_H__ |
19 | #define __GR_CTX_GK20A_H__ | 19 | #define __GR_CTX_GK20A_H__ |
20 | 20 | ||
21 | |||
22 | /* production netlist, one and only one from below */ | 21 | /* production netlist, one and only one from below */ |
23 | /*#undef GK20A_NETLIST_IMAGE_FW_NAME*/ | 22 | /*#undef GK20A_NETLIST_IMAGE_FW_NAME*/ |
24 | #define GK20A_NETLIST_IMAGE_FW_NAME GK20A_NETLIST_IMAGE_B | 23 | #define GK20A_NETLIST_IMAGE_FW_NAME GK20A_NETLIST_IMAGE_B |
24 | |||
25 | /* emulation netlists, match majorV with HW */ | 25 | /* emulation netlists, match majorV with HW */ |
26 | #define GK20A_NETLIST_IMAGE_A "NETA_img.bin" | 26 | #define GK20A_NETLIST_IMAGE_A "NETA_img.bin" |
27 | #define GK20A_NETLIST_IMAGE_B "NETB_img.bin" | 27 | #define GK20A_NETLIST_IMAGE_B "NETB_img.bin" |
@@ -146,4 +146,7 @@ struct gr_ucode_gk20a { | |||
146 | int gr_gk20a_init_ctx_vars(struct gk20a *g, struct gr_gk20a *gr); | 146 | int gr_gk20a_init_ctx_vars(struct gk20a *g, struct gr_gk20a *gr); |
147 | int gr_gk20a_init_ctx_vars_sim(struct gk20a *g, struct gr_gk20a *gr); | 147 | int gr_gk20a_init_ctx_vars_sim(struct gk20a *g, struct gr_gk20a *gr); |
148 | 148 | ||
149 | struct gpu_ops; | ||
150 | void gk20a_init_gr_ctx(struct gpu_ops *gops); | ||
151 | |||
149 | #endif /*__GR_CTX_GK20A_H__*/ | 152 | #endif /*__GR_CTX_GK20A_H__*/ |
diff --git a/drivers/gpu/nvgpu/gk20a/hal_gk20a.c b/drivers/gpu/nvgpu/gk20a/hal_gk20a.c index b3e9b0e6..f8a997e2 100644 --- a/drivers/gpu/nvgpu/gk20a/hal_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/hal_gk20a.c | |||
@@ -21,6 +21,7 @@ | |||
21 | #include "gk20a.h" | 21 | #include "gk20a.h" |
22 | #include "gk20a_gating_reglist.h" | 22 | #include "gk20a_gating_reglist.h" |
23 | #include "channel_gk20a.h" | 23 | #include "channel_gk20a.h" |
24 | #include "gr_ctx_gk20a.h" | ||
24 | 25 | ||
25 | struct gpu_ops gk20a_ops = { | 26 | struct gpu_ops gk20a_ops = { |
26 | .clock_gating = { | 27 | .clock_gating = { |
@@ -44,6 +45,7 @@ int gk20a_init_hal(struct gpu_ops *gops) | |||
44 | gk20a_init_gr(gops); | 45 | gk20a_init_gr(gops); |
45 | gk20a_init_fb(gops); | 46 | gk20a_init_fb(gops); |
46 | gk20a_init_fifo(gops); | 47 | gk20a_init_fifo(gops); |
48 | gk20a_init_gr_ctx(gops); | ||
47 | gops->name = "gk20a"; | 49 | gops->name = "gk20a"; |
48 | 50 | ||
49 | return 0; | 51 | return 0; |